AR# 46766

Spartan-6 FPGA Design Assistant - Using optimization features from third-party synthesis tools


The following Answer Record discusses how optimization features can be used from third-party synthesis tools to help optimize your design.

NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.


Some third-party synthesis tools, such as SynplifyPro,have optimization features that can help to improve performance with your design.For more information on synthesis tool settings that should be utilized,see theHDL Coding Practices to Accelerate Design PerformanceWhite Paper(WP231):

Following is a list of sections in this white paper that specifically mention the different synthesis tool settings:
  • "Maximize Block RAM Performance"
  • "Use of I/O Registers"
  • "Replicate Registers with High-Fanout"
  • "Nested If-Then-Else, Case Statements, and Combinatorial For-Loops"



Answer Number 问答标题 问题版本 已解决问题的版本
44744 Spartan-6 FPGA Solution Center N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
46745 Spartan-6 FPGA Design Assistant - Designing configurable logic structures in Spartan-6 FPGAs N/A N/A
AR# 46766
日期 12/15/2012
状态 Active
Type 综合文章