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AR# 46778

Zynq-7000 - How do I configure the PS DDRC board parameters?


How do I configure the PS DRAM Controller (DDRC) board parameters?


To properly calibrate the DDRC interface timing, you must either import an existing board profile or provide printed circuit board (PCB) delay characteristics of the specific board to be used and consider using a training algorithm. Select the DRAM Training checkboxes to enable automatic training. Not all training algorithms are available for all DDR standards.

Enter DQS to Clock Delay and Board Delay settings with the delays in nanoseconds of the PCB to be used. When you enable a specific training algorithm, Vivado/XPS uses the information in these rows to determine an initial delay value from which to begin searching. When a training algorithm is disabled or not available, the delay values are instead used to calculate a static interface timing.

The following delays should also include package delays (the calculation table below will include the Zynq-7000 package delay):

  • DQS to Clock Delay - in nanoseconds, the delay difference of each DQS path delay subtracted from the clock path delay. While negative values can be entered, they are less optimal than 0 or positive values - this infers that DQS length is equal to or shorter than the clock length. For fly-by topologies, the clock delay will be longer to some byte-lanes, resulting in a larger value to be entered.
  • Board Delay - in nanoseconds, the mid-range of all the data trace delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the mid-range of the clock delays (DDR_CK, DDR_CK_N).

The Board Delay Calculation Table is a worksheet to assist in the calculation of the DQS to Clock Delay and Board Delay parameters. Enter the mid-range of trace lengths for the group of signals listed under Length and adjust the associated Propagation Delay if necessary. The Package Length (mils) defaults are extracted from the Zynq package delays, and can be set to 0 if the Length (mm) measurement already includes the Zynq package delay. The memory package trace lengths should also be included in the Length (mm) measurement.

Vivado DDR Configuration GUI:

EDK XPS DDR Configuration GUI:

For more information, see the "Initialization and Calibration" section of the "DDR Memory Controller" chapter of the Zynq-7000 Extensible Processing Platform Technical Reference Manual (UG585).



Answer Number 问答标题 问题版本 已解决问题的版本
52540 Zynq-7000 AP SoC - Frequently Asked Questions N/A N/A
53051 Zynq-7000 AP SoC - PS DDR Controller N/A N/A
AR# 46778
日期 07/16/2014
状态 Active
Type 综合文章
  • Zynq-7000
  • EDK - 14.4
  • EDK - 14.5
  • EDK - 14.6
  • More
  • EDK - 14.7
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.2
  • Less