AR# 4685


4.1i UNISIMS - Adding the INIT attribute to VHDL/Verilog based FD models for RTL simulation?


General Description:

For RTL HDL simulation, how is the INIT attribute passed to the UNISIM

based FD models?

This feature is implemented for Alliance 3.1i and above.

Passing the INIT attribute with HDL attributes does not initialize the contents

for synthesis. The following example is written for Synplicity's Synplify. Please refer

to your synthesis vendor's documentation since all synthesis tools have their own

mechanism for passing attributes to the implementation netlist.

Another method for passing the INIT attributes to the Alliance tools is through the

use of a UCF file. For example, this statement defines the initialization string for

the code example above.



The value of the INIT string is a binary number that defines the initialization string.

Also, you can specify S which indicates Set or R for Reset.


For UNISIM RTL Verilog simulation, the INIT attribute is passed by the

defparam statement that is used to initialize contents of the FD.

module ff_init (CLK, D_IN, Q_OUT);

input CLK;

input [1:0] D_IN;

output [1:0] Q_OUT;

wire CLK_P;

BUFG A1 (.I (CLK), .O (CLK_P));

// Only for Simulation -- the defparam will not synthesize

// Use the defparam for RTL simulation.

// synthesis translate_off

defparam FD0.INIT=1'b1, FD1.INIT=1'b0;

// synthesis translate_on

// Instantaition of two FDs

// Use the xc_props attribute to pass the INIT property in Synplify

// Initialized preset flip-flop

FD FD0 (.Q (Q_OUT[0]), .D (D_IN[0]), .C (CLK_P))

/* synthesis xc_props="INIT=1" */;

// Initialized reset flip-flop

FD FD1 (.Q (Q_OUT[1]), .D (D_IN[1]), .C (CLK_P))

/* synthesis xc_props="INIT=0" */;


For VHDL RTL simulation, the INIT attribute is passed through a configuration statement

which maps the INIT generic available in the FD model. The generic is for simulation

purposes only.

library IEEE;

use IEEE.std_logic_1164.all;

library UNISIM;

use UNISIM.vcomponents.all;

entity FF_INIT is

port (Data_In: in std_logic;

Clock: in std_logic;

Data_Out: out std_logic);

end FF_INIT;

architecture STRUCT of FF_INIT is

component FD

port (Q : out std_logic;

D : in std_logic;

C : in std_logic);

end component;


myff : FD port map (D => Data_In, Q => Data_Out,

C => Clock);


configuration initialize of FF_INIT is


for all : FD use entity UNISIM.FD(FD_V)

generic map (INIT => '1');

end for;

end for;

end initialize;
AR# 4685
日期 08/09/2011
状态 Archive
Type 综合文章
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