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AR# 46866

MIG 7 Series v1.4 DDR2/DDR3 - Traffic generator flags data errors incorrectly

Description

MIG 7 Series v1.4 DDR2/DDR3 traffic generator might show false data errors in hardware and when END_ADDRESS is higher than 0x00000000_ffffffff.

解决方案

To ensure reliable data comparison and avoid false errors, the end address logic has now been updated and the error_byte and error_bit signals have been registered. These fixesare going to beincluded in the 14.1 software release.

In the meantime, the tactical patch is available for download at:
http://www.xilinx.com/txpatches/pub/applications/misc/ar46866_rev1.zip

To install the patch, extract the contents of "ar46866_rev1.zip" to the ./example_design/rtl/traffic_gen directory of the generated MIG 7 Series design (e.g., C:\my_ddr_design\example_design\rtl\traffic_gen).

NOTE: The MIG core must be generated first (prior to installing the tactical patch), otherwise the patch files will be overwritten.

Revision History

03/16/2012 - Initial release of tactical patch
AR# 46866
创建日期 03/16/2012
Last Updated 10/16/2012
状态 Active
Type 已知问题
器件
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG 7 Series