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AR# 46871

Zynq-7000 - Which IBIS models should be used for Zynq-7000 devices?

Description

Which IBIS model should I use for Zynq-7000 devices?

解决方案

The Zynq-7000 IBIS models are available on Xilinx.com under Device Models -> IBIS Models -> Zynq-7000 AP SoC -> Zynq-7000 IBIS Model:
 
http://www.xilinx.com/support/download/index.htm

The following IBIS models should be used for DDRC simulation.

Note: While the labels may differ from Vivado/PlanAhead output, the underlying model should alias to the same model:

Address/Command Signals

  • DDR_A
  • DDR_CKE
  • DDR_BA
  • DDR_ODT
  • DDR_WE_B
  • DDR_CAS_B
  • DDR_RAS_B
  • DDR_CS_B
  • DDR_DRST_B


DDR3:

       SSTL15_S_PSDDR (1.5V) / SSTL135_S_PSDDR (1.35V)

DDR2:


      SSTL18_I_S_PSDDR

LPDDR2:

      HSUL_12_DCI40_S_PSDDR

(Note: This input model assumes a 40 Ohm DCI Reference.)

Note: The DDR_DRST_B signal does NOT use the LVCMOS IOSTANDARD as the soft MIG controller uses.

Data and Clock Signals

  • DDR_DQ
  • DDR_DM
  • DDR_DQS_P
  • DDR_DQS_N
  • DDR_CK_P
  • DDR_CK_N

DDR3:

      SSTL15_T_DCI_F_PSDDR_IN40_I (1.5V) / SSTL135_T_DCI_F_PSDDR_IN40_I (1.35V) (input)

(Note: This input model assumes a 40 Ohm DCI Reference.)
 
     SSTL15_T_DCI_F_PSDDR_O (output)

DDR2:

      SSTL18_II_DCI_F_PSDDR_IN50_I (input)

(Note: This input model assumes a 50 Ohm DCI Reference.)

      SSTL18_II_DCI_F_PSDDR_O (output)

LPDDR2: 

      HSUL_12_DCI40_F_PSDDR

(Note: This input model assumes a 40 Ohm DCI Reference.)

Other PS I/O, including MIO, should use one of the high-range (HR) based I/O models, depending on the bit field settings of the individual MIO pin MIO_PIN_xx registers: IO_Type and Speed (Slow or Fast edge rate).

      HSTL_I_18_F_PSMIO    
      HSTL_I_18_S_PSMIO    
      LVCMOS18_F_8_PSMIO           
      LVCMOS18_S_8_PSMIO  
      LVCMOS25_F_8_PSMIO
      LVCMOS25_S_8_PSMIO
      LVCMOS33_F_8_PSMIO
      LVCMOS33_S_8_PSMIO
      LVTTL_F_8_PSMIO
      LVTTL_S_8_PSMIO

For details on how to use the IBIS models and package files, see (Xilinx Answer 21632).

Starting with Vivado 2014.3, the "write_ibis" command can be used to write design-specific IBIS models for Zynq.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
52540 Zynq-7000 AP SoC - Frequently Asked Questions N/A N/A
53051 Zynq-7000 AP SoC - PS DDR Controller N/A N/A
AR# 46871
创建日期 05/08/2012
Last Updated 10/14/2014
状态 Active
Type 综合文章
器件
  • Zynq-7000
Tools
  • EDK - 13.4
  • EDK - 14.1
  • EDK - 14.2
  • More
  • Vivado Design Suite - 2013.1
  • EDK - 14.5
  • EDK - 14.6
  • Less