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AR# 46879

Aurora 8B/10B v7.1/v5.3 - The core resets every 4520 USER_CLK cycles with RXNOTINTABLE errors

Description

If running the Aurora 8b/10b (v7.1/v5.3) example design, the link resets every 4520 user clock cycles due to three soft errors followed by a hard error. The soft errors are generated by the RXNOTINTABLE signal of the GTX tile, but the data is being generated by the example design.

解决方案

This behavior seems to be caused by glitches in the input (GTX_TEST) to the MGT tile from the hot plug module of the Aurora Core. The RXRESETDONE signal will deassert at the same edge as the RXNOTINTABLE errors begin with no apparent reset being applied.

The following code needs to be changed in "*_hotplug.v/vhd" to add a flip-flop on the link_reset signal in the aurora_8b10b hot plug module. This module can be found in the "src" folder in the Aurora Core.

Before Modification:

assign link_reset_0 =( (count_for_reset_r > 14'd5100) & (count_for_reset_r < 14'd10200) ) ? 1'b1 : 1'b0;
assign link_reset_1 =( (count_for_reset_r > 14'd5100) & (count_for_reset_r < 14'd16300) ) ? 1'b1 : 1'b0;

After Modification:

always @(posedge USER_CLK)
begin
link_reset_0 <=( (count_for_reset_r > 14'd5100) & (count_for_reset_r < 14'd10200) ) ;
link_reset_1 <=( (count_for_reset_r > 14'd5100) & (count_for_reset_r < 14'd16300) ) ;
end

This issuewill be fixed in the next release of the core.

Revision History:

04/13/2012 - Initial Release

AR# 46879
创建日期 04/13/2012
Last Updated 02/28/2013
状态 Active
Type 已知问题
器件
  • Virtex-6 LXT
IP
  • Aurora 8B/10B