This example design shows how to achieve QSPI (in Linear Mode) Maximum Effective Throughput with a 100 MHz SPI clock.
|Design Type||PS only|
|CPUs||Single CPU @ 720MHz|
QSPI ( in linear mode) with SPI clock @ 100MHz
DDR @ 533MHz
|Boards/Tools||ZC702 (modified to have MIO n.c. in order to enable the qspi loopback).|
|Xilinx Tools Version||EDK 14.1|
Snippet of code.
In order to achieve Linear Mode Maximum Effective Throughput with 100 MHz SPI clock, the DMA controller has been used.
This very flexible DMA can execute a few lines of microcode in order to transfer data from the Linear QSPI to DDR.
Following is an example of microcode that moves 256 Kbytes from LQSPI to DDR:
DMAMOV CCR, SB16 SS32 DB16 DS32
DMAMOV SAR, 0xFC000000
DMAMOV DAR, 0x00300000
The QSPI is set to operate in Linear Mode: single SPI flash memory, Fast read quad I/O (LQSPI_CFG = 0x82FF04EB ).
SPI reference clock: 200 MHz
SPI clock: 100 MHz (with DIV2)
The CPU is running at 720 MHz and DDR at 533 MHz.
Transfer time is calculated by counting elapsed counter ticks in the CP15 performance monitor register.
Note: I also attached an example tested on 14.2. It does not include the "transfer time" calculation, but it shows how to use the dma to read data from the qspi.
Following are the results for 1.0 silicon:
|Read mode at 100 MHZ (DIV2)||
Average PL330 transfer time to DDR
% Bandwidth Vs. theoretical
|QUAD OUTPUT - FAST READ (0x6B)||~ 31||~ 62%|
|QUAD IO - FAST READ (0xEB)||~ 36||~ 72%|
|Boards & Kits||