This answer record provides a downloadablePDF of the Debugging and Packet Analysis Guide with Downstream Port Model and PIO Example Design forVirtex-5 FPGAEndpoint Block Plus for PCI Express designs to enhance its usability.
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The documentlinked tothis answer recorddiscusses the PIO Example Design and the Downstream Port Model that come with the generation of the Virtex-5 FPGA Integrated PCI Express Block Plus Core in the CORE Generator software. The main goal of this document is to provide detailed information on the architecture of the PIO Example Design and the simulation setup consisting of the Downstream Port Model.
The PIO Example Design simulation emulates the packet transaction between a Downstream Port and an endpoint. This document describes how the initialization process takes place, how the configuration transactions are initiated by the Downstream Port Model, and how a normal memory read, memory write, and I/O read write transactions are initiated by the host. The generation of a Completion packet by the endpoint is also covered.
The latter part of the document goes through the packet analysis of the TLPs generated by theDownstream Port Model and the corresponding Completions generated by the endpoint example design. The detailed waveform analysis of the packets areprovided with the example design, which should helpyou debug your design issues associated with the Virtex-5 FPGA Integrated PCI Express Block Plus Core.
03/20/2012 - Initial Release