UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46913

Zynq-7000 Example Design - Program the PL using the Linux driver for DEVCFG

Description

This example design shows how to program the PL using the following Linux instructions and a raw binary bitstream.

mknod /dev/xdevcfg c 259 0 > /dev/null
cat system.bit.bin > /dev/xdevcfg

Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.

A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.

It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill their needs.

Limited support is provided by Xilinx on these Example Designs.

Implementation Details
Design Type PS and PL
SW Type Bootgen / Linux
CPUs Single CPU
PS Features DEVCFG
PL Cores --
Boards/Tools ZC702
Xilinx Tools Version Vivado/SDK 2015.1
Other details --

解决方案

Instructions:

In order to use the Linux driver for devcfg to program the PL, the bitstream needs to be converted to a binary. 

The BootGen tool is used for this operation.

The BootGen tool uses an input file called a "BIF" which outlines the structure of the boot image.  


An example of a BIF file is:

the_ROM_image:
{
[bootloader]<fsbl_name>.elf
<pl_bitstream_name>.bit
<u-boot_name>.elf
}


Note that the [bootloader] tag is needed to denote which ELF binary is the First Stage Boot Loader for this design. 

In addition, note that the .BIT PL bitstream line is optional if PL programming is not needed during the boot process.


Open a command line shell (for example, cmd.exe on Windows or a shell terminal in Linux) and source the Xilinx tools environment.

Bootgen is executed in the following manner:

bootgen -image <bootimage>.bif -split bin -o i BOOT.BIN

In the above example, the .BIF specified is the one created above.  

Using BootGen with the "-split" option will create binary versions of each of the input files from the .BIF and output them all as independent files rather than the usual monolithic boot image file.  

The following file is created:

<pl_bitstream_name>.bit.bin

This binary output file can be used by Linux to directly program the Zynq PL. 

Place the .BIT.BIN on an SD card and then boot into Linux. 


Once Linux is booted, mount the SD card and then create a device node for the Zynq devcfg block:

mknod /dev/xdevcfg c 259 0 > /dev/null 

Next, use the Linux "cat" command to stream the PL bitstream in the Zynq PL:

cat <path_to_storage_media>/<pl_bitstream_name>.bit.bin > /dev/xdevcfg

The PL is now programmed. 

This can be verified by observing the "DONE" LED on the board or by DEVCFG.INT_STS(PCFG_DONE_INT) register value.


NOTE 1: The -split option has been removed from Bootgen in the 2013.2 release and added back in 2013.3 release. 

To generate a separate bit swapped bit file in bin format for DEVICECFG, the promgen command line from an ISE install can be used.

promgen -p bin -data_width 32 -b -u 0x0 <design_name>.bit


NOTE 2: Starting from 2014.1 Bootgen has an option called "process_bitstream" and it will generate the BIN file which can be used for PL to configure from PS via Devcfg.

Example:

bootgen -image all.bif -w -process_bitstream bin

BIF File:

all:

{

system.bit

}

Output:

The file system.bit.bin is generated in the current working directory.


NOTE 3: In a later version of Linux Kernel the /dev/xdevcfg might be auto generated.

When you encounter "mknod: /dev/xdevcfg: File exists" warning message after running the "mknod /dev/xdevcfg c 259 0 > /dev/null" command you can just run the next command.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
51779 Zynq-7000 AP SoC - Example Designs and Tech Tips N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
47002 Zynq-7000 Debug - How do you program a bitstream using Lauterbach? N/A N/A
AR# 46913
创建日期 03/21/2012
Last Updated 07/14/2015
状态 Active
Type 综合文章
器件
  • Zynq-7000
Tools
  • Vivado Design Suite - 2015.1
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit