UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4697

F1.4, XVHDL: Assigning power mode to output signals in VHDL

Description

Keywords: XVHDL, Metamor, attribute, pwr_mode, low, std, CPLD

Urgency: Standard

General Description:
When assigning power mode in VHDL for a CPLD design using the PWR_MODE attribute in an XVHDL (Metamor) VHDL file gives the following warning:

WARNING:basnu:159 - Attribute "PWR_MODE" on "we_n" is on the
wrong type of object. Please see the "Attributes, Constraints, and Carry Logic" section of the Libraries Guide for more information on this attribute.

解决方案

The workaround is to create intermediate nodes/signals and place the
PWR_MODE attribute on the intermediate nodes/signals.

VHDL Example:

library METAMOR;
use METAMOR.attributes.all;

entity power is

port ( DISPA : out STD_LOGIC_VECTOR (6 downto 0);
DISPB : out STD_LOGIC_VECTOR (6 downto 0)
) ;
end power;

architecture fib_arch of fib is

signal mydispa, mydispb : std_logic_vector (6 downto 0);
ATTRIBUTE PWR_MODE:STRING;

ATTRIBUTE CRITICAL OF mydispa: SIGNAL IS TRUE;
ATTRIBUTE PWR_MODE OF mydispa: SIGNAL IS "LOW";

ATTRIBUTE CRITICAL OF mydispb: SIGNAL IS TRUE;
ATTRIBUTE PWR_MODE OF mydispb: SIGNAL IS "STD";
.
.
.

DISPA <= mydispa;
DISPB <= mydispb;

end power_arch ;
AR# 4697
创建日期 09/25/1998
Last Updated 01/02/2000
状态 Archive
Type 综合文章