2. 技术支持
  3. AR# 4706: MENTOR (Convert Design) - After retargetting my design, the design is empty
  4. AR# 47068: Zynq-7000 SoC - Speeds Files Revision History

AR# 47068

Zynq-7000 SoC - Speeds Files Revision History

描述

This answer record contains the Revision History for Zynq-7000 family speeds files.

解决方案

Speeds Files Revision History

1.03 Release: Description and Explanation of Changes - 14.3/2012.3

  • Updated Clocking and BUFG Blocks
  • Updated PSS Block

1.02 Release: Description and Explanation of Changes - 14.2/2012.2

  • Updated Clocking Blocks
  • Updated PSS Block

1.01 Release: Description and Explanation of Changes - 14.1/2012.1

  • Updated Clocking Blocks
  • Updated PSS Block

1.00 Release: Description and Explanation of Changes - 13.4

  • Updated Clocking blocks
  • Updated PSS block
  • Updated Interconnect blocks
AR# 47068
日期 02/01/2013
状态 Active
Type 综合文章
器件