AR# 47074

Virtex-6 Integrated Block Wrapper v1.7 for PCI Express - Cannot Write to Configuration Space Register of Root Port

描述

I am trying to access the configuration space of the Virtex-6 Integrated Block Wrapper v1.7 for PCI Express.

I am using the provided example design in Root Port configuration.

I have generated the core for VHDL.

After writing a value to a configuration register through the management interface as described in the user guide, it does not work.

解决方案

In the 'Xilinx_pcie_2_0_rport_v6.vhd' file in the 'example_design' directory, make the following changes:

From:

signal cfg_wr_rw1c_as_wr_n : std_logic;

To:

signal cfg_wr_rw1c_as_wr_n : std_logic := '1';

Revision History:
04/10/2012 - Initial Release

本答复记录是否对您有帮助？

AR# 47074
日期	03/26/2015
状态	Active
Type	综合文章
器件	Virtex-6 CXT Virtex-6 HXT Virtex-6 LXT Virtex-6 SXT
IP	Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )

的页面

AR# 47074

Virtex-6 Integrated Block Wrapper v1.7 for PCI Express - Cannot Write to Configuration Space Register of Root Port

描述

解决方案

应用

产品

开发者专区

技术支持

关于 Xilinx