I am trying to access the configuration space of the Virtex-6 Integrated Block Wrapper v1.7 for PCI Express.
I am using the provided example design in Root Port configuration.
I have generated the core for VHDL.
After writing a value to a configuration register through the management interface as described in the user guide, it does not work.
In the 'Xilinx_pcie_2_0_rport_v6.vhd' file in the 'example_design' directory, make the following changes:
signal cfg_wr_rw1c_as_wr_n : std_logic;
signal cfg_wr_rw1c_as_wr_n : std_logic := '1';
04/10/2012 - Initial Release