AR# 47167


14.1 EDK, Zynq - Why can only half of the PS DDR memory be used with MicroBlaze connected?


When enabling an AXI port on the processing_system7, the following INFO message appears. Why can only half of the PSDDR memory be used with MicroBlaze processorconnected?

INFO: You can modify the DDR address range accessed by Programmable Logic through the processing_system7 AXI slave interfaces. If MicroBlaze processoris a master on processing_system7 AXI slave interfaces, please use the top half of the address range (Base Address = 0x20000000; High Address = 0x3FFFFFFF). For all other masters, any subset of the DDR addresses can be used.


MicroBlaze can only access the upper half of the DDR address range since:

-The reset vector of MicroBlaze is fixed at address 0x0000_0000.
-Most MicroBlazetopologiesuselocal BlockRAM (LMB) to store reset and other exception vectors for minimum latency.
-The default PS DDR/OCM addressrange includes 0x0000_0000.
-EDK requires 2^n address alignment for address ranges.

Thus most MicroBlaze designs that intend to access the PS DDR range will need to modify the relevant PS AXI interface address range to the upper half of DDR. This can be acheived by modifying the associated BASEADDR parameter in the Address tab of the System Assembly View.

Note that if LMB is not used to host address 0x0000_0000, this restriction does not apply and the full DDR address range may be used.



Answer Number 问答标题 问题版本 已解决问题的版本
52540 Zynq-7000 SoC - Frequently Asked Questions N/A N/A
AR# 47167
日期 10/24/2012
状态 Active
Type 错误信息
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