When enabling an AXI port on the processing_system7, the following INFO message appears. Why can only half of the PSDDR memory be used with MicroBlaze processorconnected?
INFO: You can modify the DDR address range accessed by Programmable Logic through the processing_system7 AXI slave interfaces. If MicroBlaze processoris a master on processing_system7 AXI slave interfaces, please use the top half of the address range (Base Address = 0x20000000; High Address = 0x3FFFFFFF). For all other masters, any subset of the DDR addresses can be used.
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
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52540 | Zynq-7000 SoC - Frequently Asked Questions | N/A | N/A |
AR# 47167 | |
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日期 | 10/24/2012 |
状态 | Active |
Type | 错误信息 |
器件 | |
Tools | |
IP |