Tables 2-11, 2-12, and 2-13, of the LogiCORE IP Video Deinterlacer Product Guide v1.0 (PG017), documents that the buffer addressing and the number of bits that are to be used is dependent on the selected memory interface.
For a detailed list of LogiCORE IP Video Deinterlacer Release Notes and Known Issues, see (Xilinx Answer 41969).
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 41969 | LogiCORE IP Video Deinterlacer - Release Notes and Known Issues | N/A | N/A |
| AR# 47227 | |
|---|---|
| 日期 | 10/23/2013 |
| 状态 | Active |
| Type | 综合文章 |
| IP |
|