UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx -灵活应变. 智能.
  2. 技术支持
  3. AR# 47265: LogiCORE IP DisplayPort v3.1 (Vivado 2012.1) - Why does Synthesis fail when the target language is set to VHDL?

AR# 47265

LogiCORE IP DisplayPort v3.1 (Vivado 2012.1) - Why does Synthesis fail when the target language is set to VHDL?

描述

Why does Synthesis fail when the target language is set to VHDL?

解决方案

This is a known issue caused by Vivado incorrectly generating the VHDL wrapper.

It does not properly tie off all of the optional ports, and this causes a failure in synthesis.

This issue is fixed in Displayport 3.2 in Vivado 2012.2.

Please see (Xilinx Answer 33258) for a detailed list of LogiCORE IP DisplayPort Release Notes and Known Issues.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A
AR# 47265
日期 08/18/2014
状态 Archive
Type 综合文章
IP
  • DisplayPort
的页面