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LogiCORE IP DisplayPort v3.1 (Vivado 2012.1) - Why does Synthesis fail when the target language is set to VHDL?
Why does Synthesis fail when the target language is set to VHDL?
This is a known issue caused by Vivado incorrectly generating the VHDL wrapper.
It does not properly tie off all of the optional ports, and this causes a failure in synthesis.
This issue is fixed in Displayport 3.2 in Vivado 2012.2.
Please see (Xilinx Answer 33258) for a detailed list of LogiCORE IP DisplayPort Release Notes and Known Issues.