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AR# 47273

MIG 7 Series - How to Generate and Implement the Example Design in Vivado 2012.1-2012.2 Tools

描述

This article describes how to generate and implement the MIG 7 Series Example Design with Vivado 2012.1-2012.2 tools.

NOTE: This answer record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

Step 1 - Create a New Project

Launch the Vivado tool and create a new project in any directory.

Step 2 - Customize IP

Select the IP Catalog in the left side menu, and then under "FPGA Features and Design," select the "MIG 7 Series" IP.
Select the desired MIG 7 Series core options.

Step 3 - Generate IP

After customizing the IP, right-click on the ".xco" file under Design Sources and select Generate.
Select "All" when asked to "Choose Targets to Generate."
The instantiation template, if needed, can be found under the IP Sources tab, or to find the instantiation template in the generated directories go to:

/project_name project_name.srcs/sources_1/ip/component_name component_name.v[eo/ho]

In this example it would be:
/project_1/project_1.srcs/sources_1/ip/mig_7series_v1_6_0/mig_7series_v1_6_0.v

Step 4 - Generate the Example Design

The Example Design is not generated by default. To add the Example Design (Traffic Generator files and Example Top) to the Vivado project, MIG generates a script file, pa_gui.tcl in 2012.1 and vivado_gui.tcl in 2012.2, that can be run from the TCL console. To run this script, change directories to the location of the script file ("project_name project_name.srcs/sources_1/ip/mig_7series_v1_6_0/mig_7series_v1_6_0/example_design/par/"), and then source the file as shown here:

>> cd mig_7series/mig_7series.srcs/sources_1/ip/mig_7series_v1-5_0/mig_7series_v1_6_0/example_design/par/
>> source vivado_gui.tcl

If the MIG 7 Series design is generated with the Debug Signals enabled, the ChipScope modules will be instantiated in example_top.v. To use the Vivado GUI with the ChipScope cores included (Debug Feature enabled), users must separately generate all ChipScope supporting files before running synthesis and implementation. After sourcing vivado_gui.tcl, the ChipScope xco files will be added to the Vivado project. Users must then right-click on each of the ChipScope cores (icon.xco, ddr_ila_basic.xco, ddr_ila_wrpath.xco, ddr_ila_rdpath.xco, and ddr_vio_sync_async_out72.xco) and select "Generate". Once each of the cores has been generated, the top-level design can be run through Synthesis and Implementation.

Note: this step of manually generating each ChipScope core is only required in GUI mode.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
51635 Xilinx MIG 7 Series Solution Center - Design Assistant - Synthesis and Implementation usage and debug N/A N/A
AR# 47273
日期 10/16/2012
状态 Active
Type 解决方案中心
器件
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG 7 Series
的页面