This Answer Record forms part of the SelectIO Solution Centre (Xilinx Answer 50924).
It is intended to guide users on how to correctly set up SelectIO IOs in their design.
The following topics are covered:
General IOSTANDARD Considerations:
It is recommended that the user becomes familiar with the available I/O standards, Bank Types and I/O banking rules for their device.
From 7 Series onwards there are now multiple bank types in each device.
High Range (HR) banks aim to give the most flexibility in terms of supported I/O standards, while High Performance (HP) banks aim to give the highest performance for a smaller number of supported signaling standards.
In UltraScale+ families, High Density banks have been introduced. These have a large number of IOs across a wide range of IOSTANDARDS, but have less logic capabilities in the I/O tile.
You should have a good understanding about how many of each are available in your chosen device.
Of crucial importance is a good grasp of the I/O bank rules. Understanding what can be placed in a given bank will help you to avoid issues later on in the design flow.
Xilinx strongly recommends that you do I/O pin planning in Vivado as early as possible in the design flow.
You can create a project in pin planning mode and do a placement of your I/O before you have a complete RTL netlist.
This will allow a full set of I/O DRC checks to be run as well as SSO analysis on the pinout.
It also facilitates the creation of:
Single Ended I/O Standard settings:
Generally, single ended I/O standards like LVCMOS are used for low speed interfaces and GPIO.
These are relatively simple standards. The only concern for inputs is the VIL/VIH numbers in the data sheet.
The only settings the user can change on the output are the drive and slew.
Each family's SelectIO User Guide will enumerate the different drive settings available as well as the valid selections for SLEW.
In 7 Series there is only an option to set the slew rate to FAST or SLOW. UltraScale HP banks extend this to FAST/Medium/Slow.
In general for higher performance interface, a fast slew rate is used. However, setting the slew to FAST can also lead to reflections or increased noise issues if not properly designed.
The SLOW setting generally minimizes the power bus transients when used with non-critical signals.
The drive setting can be selected from a wide range for LVCMOS.
The user should remember that more drive strength is not always desirable as it can lead to ringing at downstream devices and reflections.
The user should always look to match the driver to the line impedance.
VREF Based I/O Standards
Xilinx supports VREF based differential inputs like SSTL and HSTL.
This allows for the support of multiple DDR memory standards.
If an SSTL18/SSTL15 input is placed in a bank, there is a requirement for VREF in that bank.
In families up to and including 7 Series, VREF pins were multi-purpose, i.e. if there was no VREF based input in a bank then the VREF site could be used as an I/O.
There is an option in 7 Series to use an internally generated VREF if there is a need to save package pins. However this internal VREF comes at the expense of higher memory interface data rates.
Xilinx has produced XAPP1087 which describes how to properly create a VREF on the board for use with high performance memory interfaces.
Since the advent of UltraScale, there have been some changes to how VREF is handled in the FPGA.
First of all the bank now has a dedicated VREF pin. The user can now opt to use the internal VREF or VREF SCAN in HP banks or drive the dedicated VREF with an on board supply.
When this internal reference is used, the dedicated pin needs to be grounded with a 500Ohm - 1Kohm resistor.
VREF_SCAN can be used in HP banks to adjust the VREF level in order to give the widest data eye. Please see (UG571) for a detailed description of this functionality.
In a bank where there is no VREF requirement, then the pin can be grounded with a 500ohm or 1K resistor, or left floating.
Differential I/O standards:
Xilinx supports multiple differential signaling standards.This includes true differential input receivers and drivers for LVDS.
For LVDS receivers there was traditionally a lot of flexibility, as the VCCO of the bank did not have to match the nominal voltage for the LVDS I/O standard.
For instance in 7 Series you could place an LVDS_25 input in a bank powered at 3.3V. Please see (Xilinx Answer 43989) for more details.
The main attribute that was programmable was the on die input differential termination. To enable DIFF_TERM you would be required to match the bank voltage to the IOSTANDARD.
Since the advent of UltraScale and UltraScale+, there have been some additional features added to differential I/O standards.
Please refer to (UG571) for more detail on these attributes.