We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47295

Soft Error Mitigation Controller - No Testbench Available when Generating Example Design in Vivado


Version Found: v3.2
Version Resolved and other Known Issues: See (Xilinx Answer 44541).

In Vivado, when right-clicking on the sem xci file in the Hierarchy view to Generate the selectable output products, the list of targets to generate includes a check box for testbench. Checking this option will not generate a testbench for simulation.


Simulation of designs that instantiate the controller is supported. In other words, including the controller in a larger project does not adversely affect ability to run simulations of functionality unrelated to the controller. However, it is not possible to observe the controller behaviors in simulation. Simulation of a design including the controller will compile, but the controller will not exit the initialization state. Hardware-based evaluation of the controller behaviors is required. For this reason, no simulation test bench is provided with the example design.

Revision History
05/08/2012 - Initial Release

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.



Answer Number 问答标题 问题版本 已解决问题的版本
44541 Soft Error Mitigation Controller - Release Notes and Known Issues for v1.1 to v3.4 N/A N/A
AR# 47295
日期 05/20/2012
状态 Active
Type 已知问题
  • Soft Error Mitigation