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AR# 47334

Floating Point Operator (FPO) v6.0 (Vivado 2012.1) - Why do I see unexpected results when using a VHDL post-synthesis simulation model?

描述

Why do I see unexpected results when using a VHDL post-synthesis simulation model?

解决方案


This is a known issue when using the Floating Point Operator (FPO) v6.0 in the Vivado Design Suite 2012.1 release.

This issue only affects VHDL Unisim model simulation and there is no impact on core functionality.

To work around this issue, the user can perform behavioral simulation, or use Verilog post-synthesis (write_verilog) model for simulation instead of the VHDL post-synthesis (write_vhdl) model.

This issue is scheduled to be fixed in Vivado Design Suite 2012.2.

For a detailed list of LogiCORE Floating Point Operator Release Notes and Known Issues, see (Xilinx Answer 29598).
AR# 47334
日期 05/04/2012
状态 Active
Type ??????
IP
  • Floating-Point Operators
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