2. 技术支持
  3. AR# 4735: A1.5/F1.5 PAR - MPPR gives reasonable results at first cost table run, but unreasonable results on subsequent cost tables.
  4. AR# 47350: MIG 7 Series DDR2/DDR3 - Synplicity fails to compile VHDL designs

AR# 47350

MIG 7 Series DDR2/DDR3 - Synplicity fails to compile VHDL designs

描述

Version Found: v1.5
Version Resolved and other Known Issues: See(Xilinx Answer 45195).

Synplicity fails to compile the MIG 7 Series DDR2/DDR3 VHDL designs.

The following error message is received:

@E: CD629 :"./mig_7series_v1_5/user_design/rtl/phy/ddr_phy_top.vhd":625:5:625:6|Failed to evaluate generic ctl_bank

解决方案

This is an issue with the Synplify Pro VHDL compiler and is scheduled to be fixed in a future version of Synplify.

There is no workaround for Synplify, so XST must be used as a workaround if the VHDL design is required.
AR# 47350
日期 08/26/2014
状态 Active
Type 已知问题
器件
IP