Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 45195).
If the synthesis option "KEEP_HIERARCHY" is set to "YES" the MIG 7 Series designs will fail during the MAP stage with an error similar to the following:
is driven by
ne_B/ddr_byte_group_io/dqs_gen.oddr_dqs (Q pin) and
ne_B/ddr_byte_group_io/dqs_gen.oddr_dqsts (Q pin), but they are not all in the same level of hierarchy. Please ensure that any OBUF(T)DS with differential IOSTANDARD that is driven by a register or OSERDES exists in the same level of hierarchy as its drivers. This may be achieved by setting KEEP_HIERARCHY=FALSE on those levels of hierarchy separating the OBUF(T)DS from its drivers.
Setting "KEEP_HIERARCHY" to "YES" is not supported for MIG 7 Series designs.
To work around the issue, KEEP_HIERARCHY=NO can be set locally for the MIG design.
Here is some example syntax for setting the KEEP_HIERARCHY option locally in the RTL:
KEEP_HIERARCHY Verilog Example:
(* keep_hierarchy = "no" *) example_design u0_example_design (.dq(dq), .dqs)dqs), ...);
KEEP_HIERARCHY VHDL Example:
attribute keep_hierarchy : string;
attribute keep_hierarchy of u0_example_design : label is "no";