AR# 47385


MIG 7 Series RLDRAMII - Timing violations may occur when Debug Signals feature is enabled


Version Found: v1.5
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

When implementing the MIG 7 Series RLDRAMII design with the "Debug Signals" feature enabled, timing violations might be seen.


Example Timing Errors:

109037 paths analyzed, 22057 endpoints analyzed, 74 failing endpoints
74 timing errors detected. (74 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 4.749ns.
Slack (setup path): -0.305ns (requirement - (data path - clock path skew + uncertainty))
Source: u_mig_7series_v1_4/u_rld_memc_ui_top_std/gen_ui_fifos.u_rld_ui_top/u_usr_wr/gen_wdf0[0].u_wdf_data0/FIFO36E1 (RAM)
Destination: u_traffic_gen_top/u_memc_traffic_gen/memc_control/addr_r_19 (FF)
Requirement: 4.444ns
Data Path Delay: 4.307ns (Levels of Logic = 4)
Clock Path Skew: -0.374ns (1.256 - 1.630)
Source Clock: clk rising at 0.000ns
Destination Clock: clk rising at 4.444ns
Clock Uncertainty: 0.068ns

These timing errors only occur when the "Debug Signals" feature is enabled.

To temporarily work around this issue, disable the "Debug Signals" feature and rerun implementation.
AR# 47385
日期 08/26/2014
状态 Active
Type 已知问题
器件 More Less
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