This example design allocates 4K of block RAM attached to the M_AXI_GP0 and monitored by the ChipScope tool.
The software then treats the memory as a "shareable device" or "strongly-ordered," and a Vivado Logic Analyzer shot provides the distance between two consecutives BVALID signals on the AXI port for THROUGHPUT.
Implementation Details | |||
Design Type | PS and PL | ||
SW Type | Standalone | ||
CPUs | Single CPU @ 666.67MHz | ||
PS Features | MMU | ||
PL Cores | BRAM, ILA | ||
Boards/Tools | ZC702 | ||
Xilinx Tools Version | Vivado 2015.1 | ||
Other details | FCLK @ 150MHz | ||
Address Map | |||
Base Address | Size | Bus Interface | |
Block RAM | 0x41200000 | 4K | S_AXI |
Files Provided | |||
zc702_ar47406_v2015_1.zip | Archived Vivado IPI project. | ||
xdmaps_example_w_intr.c | Snippet of code. | ||
zc702_ar47406.tcl | TCL script to create the IPI block design | ||
Block Diagram | |||
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Step-by-Step Instructions
Expected Results
Throughput | |||
Type | FCLK Cycles | CPU Cycles | Time (nS) |
Strongly-ordered | |||
Shareable device | 16 | 0 | 106 |
文件名 | 文件大小 | File Type |
---|---|---|
xdmaps_example_w_intr.c | 12 KB | C |
zc702_ar47406.tcl | 9 KB | TCL |
zc702_ar47406_v2015_1.zip | 135 KB | ZIP |
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
51779 | Zynq-7000 SoC - Example Designs and Tech Tips | N/A | N/A |
AR# 47406 | |
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日期 | 05/18/2018 |
状态 | Active |
Type | 综合文章 |
器件 | |
Tools | |
Boards & Kits |