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AR# 47411

LogiCORE IP Serial RapidIO Gen2 v1.4 (Vivado 2012.1) - Malformed SRIO synthesis netlist when Hierarchy is set to 'rebuilt'

描述

When generating LogiCORE IP Serial RapidIO Gen2 v1.4 core in Vivado Design Suite 2012.1 with default Hierarchy set to 'rebuilt', this results in a malformed SRIO synthesis netlist.

解决方案


This is a known issue and is scheduled to be fixed in a future release of the core.

To work around this issue, click on the Synthesis Settings in the left pane, then change -flatten_hierarchy from 'rebuilt' to 'none'.

NOTE: For other known issues please check (Xilinx Answer 47190).

Revision History
05/08/2012 - Initial Release
AR# 47411
日期 05/07/2012
状态 Active
Type ??????
Tools
  • Vivado - 2012.1
IP
  • Serial RapidIO
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