AR# 47499


SelectIO Design Assistance - Setting up on-chip termination in software


There are three types of on-chip termination,

  1. DCI

How do you set these up in software?



In order to select DCI in software, the DCI specific IOSTANDARD needs to selected. 

For example, for SSTL15 with DCI, use the SSTL15_DCI IOSTANDARD. 

The device family user guide normally specifies what enabling this termination type does. In the case of SSTL15, this will enable split termination on the input.

Note: Using DCI has a hardware requirement that the Vrp/Vrn reference resistors needs to be populated on the board. The values and requirements for Vrp/Vrn are detailed in the device SelectIO User Guide. 

Some DCI IOSTANDARDs no not require the reference resistors and this is also documented in the device SelectIO User Guide.

The reference resistors can be shared across adjacent banks if compatible IOSTANDARDs are used. This is called DCI cascading.

For further explanation of DCI cascading and the requirement for compatibility for DCI cascading, see the SelectIO User Guide for your device.

In order to set up the DCI cascade in software, add the DCI_CASCADE constraint to the UCF.

The first bank number is the master and subsequent banks that are listed are the slave banks. 

The Master bank is the bank with the Vrp/Vrn connected.

CONFIG DCI_CASCADE = "<master> <slave1> <slave2> ...";

CONFIG DCI_CASCADE = "11 13 15 17";

For newer families the equivalent XDC constraint is:

set_property dci_cascade {11} [get_iobanks 13 15 17]
The master bank is specified first and then the slave banks are listed afterwards.

For further information on DCI cascading see (Xilinx Answer 38913).

(Xilinx Answer 47145) discusses the supported VRP/VRN resistor values for 7 Series devices.

(Xilinx Answer 11794) discusses the power ratings for the reference resistors.


For details on how to setup DIFF_TERM in families up to and including 7 Series, please see (Xilinx Answer 37171).

7 Series devices support Bi-directional LVDS. (Xilinx Answer 62063) describes how the DIFF_TERM is affected.

For UltraScale Architectures, the Differential input termination is enabled using either the DIFF_TERM or the DIFF_TERM_ADV attributes.

  • DIFF_TERM = TRUE automatically maps to DIFF_TERM_ADV = TERM_100
  • DIFF_TERM = FALSE automatically maps to DIFF_TERM_ADV = TERM_NONE (default)

The allowed values for DIFF_TERM_ADV attribute are:

  • DIFF_TERM_ADV = TERM_NONE (default)

The DIFF_TERM_ADV attribute uses the following syntax in the XDC file:

set_property DIFF_TERM_ADV value [get_ports port_name]

Care needs to be taken when targeting UltraScale and using this attribute. Prior to the 2016.1 release, some customers reported it not being correctly applied to UltraScale devices.

Please see (Xilinx Answer 67219) for more details.


Uncalibrated input and output termination can be set in the Vivado GUI or via the XDC file.

Please see the SelectIO user guide for the device you are using to understand what uncalibrated termination is available.

Note: Spartan-6 is the only family that supports IN_TERM and OUT_TERM.

7 Series High Range banks support IN_TERM.

In UltraScale there is support for uncalibrated input termination.



Answer Number 问答标题 问题版本 已解决问题的版本
47225 SelectIO Design Assistant - How to Terminate a Transmission Line N/A N/A


AR# 47499
日期 06/02/2017
状态 Active
Type 综合文章
器件 More Less
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