The CPU has a Store Buffer with merging capabilities within a cache line for Normal Memory regions. The buffer continues to merge data as long as the write accesses are performed to the same cache line. The Store Buffer has a small counter to push the data out to memory after a period of time to provide external visibility of the stores. The issue is that the counter is reset each time new data is merged. If a software code sequence is looping, and continues writing data in the same cache line repeatedly, the external visibility of the written data is potentially delayed indefinitely.
Minor. This issue can create performance issues, or worst-case, a live-lock scenario, in case the external agent relies on the automatic visibility of the written data in a finite amount of time.
Insert a DMB operation after the faulty write operation in code sequences which may be affected by this erratum, in order to ensure the visibility of the written data by any external agent.
Systems that use one or both processors.
|Device Revision(s) Affected:||All, no plan to fix. Refer to Zynq-7000 Device Advisory Master Answer Record|
The issue can only happen on Normal Memory regions. Two example scenarios are described below, which can trigger the issue:
The recommended work-around is to insert a DMB operation after the write operation(s) continually being held in the store buffer. This is done to ensure the visibility of the written data to any external agent. User has to insert a memory barrier, wherever he sees this issue.