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AR# 47557

Zynq-7000 AP SoC, APU - Sticky Pipeline Advance Bit Is Not Supported

描述

The Sticky Pipeline Advance bit in the DBGDSCR register enables the debugger to detect whether the processor is idle. The CPU does not implement accesses to DBGDRCR[3] via the debug APB interface, so the debugger is unable to clear the Sticky Pipeline Advance bit.

解决方案

Impact:

Minor. The Sticky Pipeline Advance bit concept is unusable.

Work-around:

None.

Configurations Affected:

Systems that use one or both ARM processors.

Device Revision(s) Affected:
All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences.

Description Details

The Sticky Pipeline Advance register (bit 25 of the DBGDSCR register) enables the debugger to detect whether the processor is idle. This bit is set to 1 every time the processor pipeline retires one instruction. A write to DBGDRCR[3] clears this bit. The issue is that the Cortex-A9 does not implement any debug APB access to DBGDRCR[3] to clear the bit.

Impact Details

Minor. Due to the issue, the Sticky Pipeline Advance bit in the DBGDSCR cannot be cleared by the external debugger.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47916 Zynq-7000 AP SoC 器件:芯片修订差异 N/A N/A
AR# 47557
日期 06/04/2013
状态 Active
Type 设计咨询
器件
  • Zynq-7000
  • Zynq-7000Q
  • XA Zynq-7000
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