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AR# 47569

Zynq-7000 AP SoC, Boot - PS-PL AXI Interfaces are Enabled upon Completion of the BootROM

描述

The AXI interfaces between PS and PL are enabled upon completion of the BootROM. Software must assert the AXI interface resets early in the execution of the FSBL. Software must always use proper reset and configuration procedures starting-up the PL AXI interfaces.

解决方案

Impact: Trivial. You should never assume that the AXI interfaces are enabled and always use proper procedures when configuring and starting the PL.

Work-around: Restore the SLCR.FPGA_RST_CTRL register to its reset value early in the first stage boot loader.

Configurations Affected: All.

Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences

Restore the SLCR.FPGA_RST_CTRL register to its reset value early in the first stage boot loader.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47916 Zynq-7000 AP SoC 器件:芯片修订差异 N/A N/A
AR# 47569
日期 06/05/2013
状态 Active
Type 设计咨询
器件
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q
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