The setup timing for MI is dependent on the SPI reference clock period when operating the SPI interface in master mode. It is always equal to one reference clock period.
Impact: |
Trivial. Satisfying the new setup requirements guarantees not to have issues. |
| Work-around: | As long as the reference clock values are known before designing the board and timing is met with respect to a setup equal to the period of the slowest possible reference clock, there is not going to be any issues. |
| Configurations Affected: | Systems that use the SPI controller in master mode. |
| Device Revision(s) Affected: | Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences |
Note:
The SPI_REF_CLK clock frequency must be greater than the CPU_1x clock frequency.
For GES devices, the SPI_REF_CLK clock frequency must be less than or equal 125 MHz.
For Production devices, the SPI_REF_CLK clock frequency must be less than or equal 200 MHz.
Ensure that your final design meets these constraints.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 47916 | Zynq-7000 AP SoC 器件：芯片修订差异 | N/A | N/A |
| AR# 47579 | |
|---|---|
| 日期 | 11/22/2013 |
| 状态 | Active |
| Type | 设计咨询 |
| 器件 |
|