We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47593

Zynq-7000 AP SoC, Boot - During NOR Boot the MIO 2 and MIO 14 pins are Inadvertently Configured by the BootROM


In NOR Boot mode, MIO 2 and MIO 14 are configured by the BootROM. These pins are not used by the SRAM/NOR interface.MIO 2 is configured as an output and MIO 14 as an input. In a successful boot, these MIO configurations are maintained until changed by FSBL or some other later process.


Impact: Minor. MIO 14 is set as an input and it is ignored during BootROM execution, therefore there is no harmful effect. MIO 2 will be driven to both 0 and 1 states during BootROM execution.

Work-around: There is no work-around. If using NOR boot mode, the board design should use MIO 2 for purposes that can tolerate this pin being driven during BootROM execution.

Configurations Affected: Systems that utilize NOR Boot mode and use MIO 2.

Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.



Answer Number 问答标题 问题版本 已解决问题的版本
52538 Zynq-7000 AP SoC - Boot and Configuration N/A N/A
AR# 47593
日期 10/22/2012
状态 Active
Type 设计咨询
  • Zynq-7000