2. 技术支持
  3. AR# 4760: 4.1i XC4000E MAP - To control whether a BUFGP or a BUFGS is used, a BUFG must be LOC'd before MAP.
  4. AR# 47606: Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - ECRC support in IES Silicon

AR# 47606

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - ECRC support in IES Silicon

描述

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The Virtex-7 FPGA Integrated Block For PCI Express v1.1 core does not support ECRCin IES Silicon.

解决方案

The End-to-End CRC (ECRC) feature cannot be enabled on a per function basis for users targeting IES silicon. The ECRC capability must be enabled or disabled identically for all enabled functions. This restriction applies to users targeting IES silicon.This is a known issue and will be fixed in a future release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/08/2012 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47441 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 47606
日期 05/20/2012
状态 Active
Type 已知问题
IP