UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx -灵活应变. 智能.
  2. 技术支持
  3. AR# 47610: Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Address Aligned Mode Support in Default Example Design

AR# 47610

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - Address Aligned Mode Support in Default Example Design

描述

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The default example design generated with the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 core does not support Address Aligned mode.

解决方案

The alignment mode is configurable within the CORE Generator interface. Address Aligned mode is not supported with the PIO example design. This is a known issue and will be fixed in a future release of the core.

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/08/2012 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47441 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 47610
日期 03/05/2013
状态 Active
Type 已知问题
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
的页面