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  3. AR# 47626: 7 Series Integrated Block for PCI Express v1.5 (ISE 14.1/Vivado 2012.1) - VHDL Simulation Support for Endpoint Configuration

AR# 47626

7 Series Integrated Block for PCI Express v1.5 (ISE 14.1/Vivado 2012.1) - VHDL Simulation Support for Endpoint Configuration

描述

Version Found: v1.5
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

Can I use "Cadence Incisive Enterprise Simulator (IES)" and "Synopsys VCS and VCS MX" simulators to perform VHDL simulation of 7 Series Integrated Block for PCI Express v1.5 core?

解决方案

7 series Integrated Block for PCI Express v1.5 core currently supports all three simulators mentioned below. However, VHDL simulation is supported only with Mentor Graphics ModelSim. Verilog simulation is supported with all three simulators in the list below.

Cadence Incisive Enterprise Simulator (IES) [Verilog Simulation Only]
Synopsys VCS and VCS MX [Verilog Simulation Only]
Mentor Graphics ModelSim [Verilog/VHDL Simulation]

Update for 7 series Integrated Block for PCI Express v1.6 core : The above limitation still exists in v1.6. However, v1.6 now supports XSIM (in Vivado) in Verilog; VHDL is not supported.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

07/25/2012 - Updated for v1.6 core
05/14/2012 - Updated for v1.5 core
05/10/2012 - Clarification on VHDL/Verilog simulation support
05/08/2012 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40469 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 47626
日期 03/01/2013
状态 Active
Type 已知问题
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