AR# 47654

AXI Video Direct Memory Access (VDMA) - Release Notes and Known Issues

This Release Note and Known Issues Answer Record is for the AXI VDMA and contains the following information:

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025).

General Information

New Features

Description	Core Version
Resource optimization	5.04.a
Default value of C_MM2S_SOF_ENABLE and C_S2MM_SOF_ENABLE changed from 0 to 1	5.03.a
Improved behavior during frame size and line size mismatch errors with separate status bits for SOF_EARLY, SOF_LATE, EOL_EARLY, and EOL_LATE errors on the S2MM channel	5.02.a
S2MM channel will never halt on line size mismatch errors in all modes including non-flush and free-run mode	5.02.a
MM2S will output Start-of-Frame on TUSER(0) in all modes including free-run mode	5.02.a
Added two new GenLock modes called Dynamic GenLock Master and Dynamic GenLock Slave	5.01.a
Integer byte data width support on streaming interface of MM2S and S2MM channel	5.01.a
External frame sync and flush enable/disable made independent for both channels by enhancing C_USE_FSYNC and C_FLUSH_ON_FSYNC parameter definitions (maintaining full backward compatibility)	5.01.a

Resolved Issues

Description	Core Version
Genlock Source bit in control register not set by driver (Xilinx Answer 53331)	5.04.a
Incorrect addressing after size mismatch error (Xilinx Answer 52479)	5.03.a
Incorrect TIG propagation in EDK (Xilinx Answer 46044)	5.01.a

Known Issues

The following table correlates the core version to the first ISE design tools release version in which it was included.

ISE/Vivado Design Tools Version	Core Version
14.4/2012.4	5.04.a
14.3/2012.3	5.03.a
14.2/2012.2	5.02.a
14.1/2012.1	5.01.a

本答复记录是否对您有帮助？

Answer Number	问答标题	问题版本	已解决问题的版本
52479	AXI VDMA v5.02.a - Incorrect addressing after size mismatch error	N/A	N/A
46044	LogiCORE IP AXI VDMA 设计咨询 - EDK 中的错误 TIG 传播	N/A	N/A
54878	LogiCORE IP AXI Video Direct Memory Access - Throughput/Bandwidth Limitations	N/A	N/A
54934	LogiCORE IP AXI Video Direct Memory Access (VDMA) - Throttling, frame size errors (SOF), and/or unexpected TKEEP behavior	N/A	N/A
55183	LogiCORE IP AXI Video Direct Memory Access v6.0 - Post-synthesis netlist simulation errors targeting defense grade or low power devices	N/A	N/A
55218	LogiCORE IP AXI Video Direct Memory Access - Horizontal shear/shift in output video	N/A	N/A
55221	LogiCORE IP AXI Video Direct Memory Access - Low frame rate/choppy video	N/A	N/A
53281	LogiCORE IP AXI Video Direct Memory Access - Recommendations for handling FSYNC	N/A	N/A
53331	LogiCORE IP AXI Video Direct Memory Access v5.03.a - Genlock Source bit in control register not set by driver	N/A	N/A

AR# 47654
日期	09/16/2013
状态	Active
Type	已知问题
器件	Artix-7 Kintex-7 Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-6Q Virtex-6QL Virtex-7 Zynq-7000 More Less
Tools	ISE Design Suite - 14.1 PlanAhead - 14.1 Vivado Design Suite - 2012.1
IP	AXI Video Direct Memory Access