AR# 47657: 2012.1 IP Packager - "Could not find synthesis files on IP" for packaged IP
2012.1 IP Packager - "Could not find synthesis files on IP" for packaged IP
When I generate my packaged IP in the CORE Generator tool, the following errors occur:
"Applying external generics to 'my_core_v1_0'... Finished delivering C-model simulation files. Delivering associated files for 'my_core_v1_0'... Delivered 5 files into directory /project_directory/my_core_src_v_test/ise_cg/ipdir/tmp/_cg/my_core_v1_0 WARNING:sim - No model name for synthesis of ':ise.xilinx.com:synthesis.rtl', defaulting to 'root'. Generating implementation netlist for 'my_core_v1_0'... INFO:sim - Pre-processing HDL files for 'my_core_v1_0'... ERROR:sim - Could not find synthesis files on IP ERROR:sim - Failed executing Tcl generator. ERROR:sim - Failed to generate 'my_core_v1_0'. Failed executing Tcl generator.
ERROR:sim:877 - Error found during execution of IP 'My Core v1.0'"
The external IP was packaged as a unified IP with 'set_param ipx.enableCoreGen true'.
IP Packager automatically inferred it as synthesis delivery for both the Vivado and CORE Generator tools. Since I wanted the core to be delivered as a source core in the CORE Generator tool, I removed the xilinx_cgverilogsynthesis group, then added the xilinx_cgverilogsourcedelivery group in the rdi_packip.tcl file as follows: