AR# 47657


2012.1 IP Packager - "Could not find synthesis files on IP" for packaged IP


When I generate my packaged IP in the CORE Generator tool, the following errors occur:

"Applying external generics to 'my_core_v1_0'...
Finished delivering C-model simulation files.
Delivering associated files for 'my_core_v1_0'...
Delivered 5 files into directory
WARNING:sim - No model name for synthesis of '', defaulting to 'root'.
Generating implementation netlist for 'my_core_v1_0'...
INFO:sim - Pre-processing HDL files for 'my_core_v1_0'...
ERROR:sim - Could not find synthesis files on IP
ERROR:sim - Failed executing Tcl generator.
ERROR:sim - Failed to generate 'my_core_v1_0'. Failed executing Tcl generator.

ERROR:sim:877 - Error found during execution of IP 'My Core v1.0'"

The external IP was packaged as a unified IP with 'set_param ipx.enableCoreGen true'.

IP Packager automatically inferred it as synthesis delivery for both the Vivado and CORE Generator tools. Since I wanted the core to be delivered as a source core in the CORE Generator tool, I removed the xilinx_cgverilogsynthesis group, then added the xilinx_cgverilogsourcedelivery group in the rdi_packip.tcl file as follows:
ipx::remove_file_group {xilinx_cgverilogsynthesis} $component
ipx::add_file_group -type {cg:verilog:source_delivery} {xilinx_cgverilogsourcedelivery} $component
ipx::add_default_generators $component

It seems to call generators for synthesis delivery.


This issue is to be fixed in Vivado Design Suite 2012.2.

You could also update the generators by first removing all of the generators, then re-add the generators:

Note that you should need to call the ipx::add_default_generators command only once at the end.
AR# 47657
日期 05/07/2012
状态 Archive
Type 已知问题
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