Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)
For the Virtual Function Configuration Space, the optional AER Correctable Error Status register Header Log Overflow Status bit is not supported.
NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Revision History
05/08/2012 - Initial release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 47441 | Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 | N/A | N/A |
| AR# 47668 | |
|---|---|
| 日期 | 02/05/2013 |
| 状态 | Active |
| Type | 已知问题 |
| IP |
|