AR# 47695

LogiCORE IP Tri-Mode Ethernet MAC - Release Notes and Known Issues for All AXI Interface Versions


This answer record contains the Release Notes for the LogiCORE IP Tri-Mode Ethernet MAC Core and includes the following:

  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide.


New Features in v5.5 Core

  • ISE 14.4 design tools support
  • Vivado 2012.4 design tools support
  • Updates to Artix and Zynq devices receive clocking to use IDELAYs instead of PLL

Supported Devices in v5.5 Core

  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 Lower Power XC LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XQ LX/LXT

Note: For a complete part and package support list, please check the Xilinx CORE Generator interface (under 'Supported Families') for the Tri-Mode Ethernet MAC Core.

For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.

General Known Issues

This table correlates the core version to the first ISE or Vivado design tools release version in which it was included.

Core Version ISE Tools Version Vivado Tools Version
v5.5 ISE 14.4 2012.4
v5.4 ISE 14.2 2012.2
v5.3 ISE 14.1 2012.1
v5.2 ISE 13.4 NA
v5.1 ISE 13.1 NA

The following table provides known issues for the Tri-Mode Ethernet MAC core, starting with v5.1, initially released in ISE Design Suite 13.1.This is the first version to support 7 series devices and have an AXI interface. For earlier versions of the core using the legacy user interface, please refer to the IP Release Notes Guide for the release notes answer record by version.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Article Number
Article Title
Version Found
Version Resolved
(Xilinx Answer 54785) IFG Adjust values smaller than 9 not used when core is generated with half duplex support v5.5 v6.0
(Xilinx Answer 53360) Multiple pause frame requests can result in a corrupted pause quanta being output v5.4 v5.5
(Xilinx Answer 52556) Frames within 12 bytes of the max frame size could get marked bad v5.4 v5.5
(Xilinx Answer 53521) RGMII_TX_ER incorrect timing at 10/100 speeds v5.4 v5.5
(Xilinx Answer 53520) Very Small Runt frames can be incorrectly marked good v5.4 v5.5
(Xilinx Answer 40028) Virtex-6 FPGAs - Meeting GMII and RGMII setup and hold times v5.1 N/A
(Xilinx Answer 35336) Spartan-6 FPGAs - Meeting GMII setup and hold times v5.1 N/A
(Xilinx Answer 50860) ISE - 7-Series - Input Timing Violations may be seen in the Example design v5.4 v5.5
(Xilinx Answer 50321) VHDL - 1G - RGMII - BUFGMUX Instantiation Results in Synthesis Errors v5.3 v5.4
(Xilinx Answer 47896) address_decode.v errors out during Synplify Synthesis v5.3 v5.4
(Xilinx Answer 47700) Invalid Reads from the AVB PTP Tx Buffer v5.2 v5.3
(Xilinx Answer 45527) UCF changes needed to target KC705 RevC/RevD v5.1 v5.3
(Xilinx Answer 45724) Targeting Spartan-6 and Virtex-6 Q-grade devices v5.1 v5.3
(Xilinx Answer 46167) Example Design UCF and Implementation Scripts are missing v5.2 v5.2rev1
(Xilinx Answer 42847) Example Design fail in BitGen when targeting Virtex-7 or Kintex-7 devices v5.1 v5.2
(Xilinx Answer 42089) ERROR:NgdBuild:973 - The temac symbol is not supported v5.1 v5.2
(Xilinx Answer 42926) Error Invalid target device when running 7-Series Example design in 13.2 v5.1 v5.2

Vivado Design Suite Specific Known Issues

Article Number
Article Title
Version Found
Version Resolved
(Xilinx Answer 54165) Timing failure seen when core generated without address filter v5.5 not resolved
(Xilinx Answer 54163) Windows - core xdc file is not correctly loaded after opening the Implemented design v5.5 not resolved
(Xilinx Answer 47733)
Ethernet AVB option not supported in Vivado Design Suite 2012.1
(Xilinx Answer 47666)
Vivado - Guidance for Simulating Ethernet IP cores



Answer Number 问答标题 问题版本 已解决问题的版本
47733 LogiCORE IP Tri-Mode Ethernet MAC v5.3 - Ethernet AVB option not supported in Vivado Design Suite 2012.1 N/A N/A
AR# 47695
日期 03/06/2013
状态 Active
Type 版本说明