AR# 47698


LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) - Release Notes and Known Issues for Versions 2.x


This answer record contains the Release Notes for the LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) and includes the following:

  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.

For Ten Gigabit Ethernet PCS/PMA v3.0 and later Release Notes, see (Xilinx Answer 54669).


New Features in Latest v2.6 Core

  • 14.4 ISE Design Suite support
  • 2012.4 Vivado Design Suite support
  • General Reset and Constraint Improvements

Supported Devices in Latest v2.6 Core

  • Virtex-6 HXT
  • Kintex-7 FFG packages -2L,-2,-3 speed grade
  • Virtex-7 -2L,-2,-3 speed grade

NOTE: For a complete part and package support list, please check the Xilinx CORE Generator interface (under 'Supported Families') for the Ten Gigabit Ethernet PCS/PMA Core.

For the previous version "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.

Core Versions

This table correlates the core version to the first ISE or Vivado tools release version in which it was included.

ISE Tool
Vivado Tool
v2.6rev3ISE 14.7NA
v2.6rev2ISE 14.6NA
v2.6rev1(Xilinx Answer 53777)NA
v2.6ISE 14.42012.4
v2.5ISE 14.32012.3
v2.4ISE 14.22012.2
v2.3ISE 14.12012.1
v2.2ISE 13.3NA
v2.1ISE 13.1NA

7 Series Transceiver Silicon Support

This table shows the latest version of the core to support different 7 Series silicon revisions.

GTX GES/Production SiliconGTH Initial ES SiliconGTH General ES SiliconGTH Production Silicon
Latest Core Versionv2.6rev3v2.6v2.6
See (Xilinx Answer 52611)

General Known Issues

The following table provides known issues for the Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) core, starting with v2.1, initially released in ISE Design Suite 13.1.

This is the first version to support 7 Series devices. For earlier versions of the core please refer to IP Release Notes Guide for the release notes answer record by version.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record
Version Found
Version Resolved
(Xilinx Answer 57987)10GBASE-KR Support - Update to Vivadov2.6NA
(Xilinx Answer 58069)Configuration Vector - 125us timer not initialized correctly in example designv2.6Work-around in answer record
(Xilinx Answer 57847)Update to RX Elastic Buffer to avoid possible underflow, latency increasedv2.6v2.6rev3
(Xilinx Answer 57503)
Virtex-7 GTH - Attribute Updates for Production Silicon
(Xilinx Answer 55676)7 Series - PRBS31 - DRP access to the GTX transceiver PRBS31 error counter could interfere with MDIO interface if usedv2.6v2.6rev2
(Xilinx Answer 55728)
7 Series - PRBS31 - Core DRP access to the GTH transceiver PRBS31 error counter should not be used v2.6v2.6rev2
(Xilinx Answer 53777)7 Series - DRP Read and Writes not initiated for Training interface or PRBS testing v2.6v2.6rev1
(Xilinx Answer 53974)Incorrect version number in core version info registerv2.6v2.6rev1
(Xilinx Answer 52611)7 Series - GTH Transceivers - Updated RXCDR attribute for targeting GES silicon v2.5Work-around in
answer record
(Xilinx Answer 53443)7 Series - TX FAULT and Signal Detect inputs from SFP do not need to connected to both rx and tx reset logic v2.5Work-around in
answer record
(Xilinx Answer 52137)7 Series - ISE 14.x - small setup violations sometimes seen v2.5not resolved
(Xilinx Answer 52520)7 Series - xco file for 7 Series Transceiver wizard can not be directly used to regenerate wrapper files provided with corev2.5not resolved
(Xilinx Answer 52517)7 Series - 10GBASE-KR - Training zero coefficient could get incorrectly set to high value v2.5v2.6
(Xilinx Answer 52537)7 Series - Block lock FSM could get stuck low if GT reset or unstable clock seen by cable pull detection logicv2.4 rev2 v2.6
(Xilinx Answer 52236)7 Series - Block lock FSM requires one extra good/bad code v2.4v2.5
(Xilinx Answer 52240)7 Series - 10GBASE-KR - Updates to Training block needed for TX output training by the far-end device to complete v2.4v2.5
(Xilinx Answer 51451)7 Series - Transmit bit errors might be seen out of reset v2.4v2.4rev3
(Xilinx Answer 51282)7 Series Devices - Updated needed to reset/initialization logic for cable pull/ RX data input not present v2.4v2.4rev2
(Xilinx Answer 50861)ISE - 7 Series Devices - Occasional timing errors seen v2.4not resolved
(Xilinx Answer 50792)7 Series Devices - Updates needed to Initialization logicv2.3v2.4
(Xilinx Answer 47128)Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Siliconv2.3v2.4
(Xilinx Answer 50790)7 Series Devices - Using Link Training for 10GBASE-KR v2.3NA
(Xilinx Answer 50788) Updates needed to example design UCF v2.3v2.4
(Xilinx Answer 50356)10GBASE-KR - Training Interface - Read data delayed by one clock cycle for 802.3 registersv2.3v2.3rev2
(Xilinx Answer 47894)Kintex-7 Devices - BUFH may need to drive MMCM inputv2.3v2.4
(Xilinx Answer 47943)In Asynchronous Systems the RX Elastic Buffer Can Incorrectly Empty v2.3v2.3rev1
(Xilinx Answer 46912)Targeting General ES silicon for 7 series Devices v2.2 v2.3
(Xilinx Answer 46053) Kintex-7 FPGA example design does not place v2.2 v2.3
(Xilinx Answer 43591)Virtex-6 FPGA GTH Transceivers - Lane powerdown can cause burst of errors in the Quad v2.2 v2.3
(Xilinx Answer 44470)Virtex-6 HXT - Incorrect arbitration logic in the management port v2.2 v2.3
(Xilinx Answer 40897) Xs are seen in ModelSim 6.6c functional or timing simulationv2.1 NA
(Xilinx Answer 40555) 7 Series Devices - Occasional timing errors seen v2.1 v2.2
(Xilinx Answer 42675)7 Series Transceiver Wrapper - GTX Port Name Changes in ISE 13.2 v2.1 v2.2
(Xilinx Answer 42849) Example Design fail in BitGen when targeting Virtex-7 or Kintex-7 devices v2.1 v2.2
(Xilinx Answer 43703) Virtex-6 GTH - Update RXBUFRESET Initialization Sequence and BUFFER_CONFIG_LANEx Attribute Values in GTH Wrapper filesv2.1 v2.3

Vivado Design Suite Specific Known Issues

Answer Record
Version Found
Version Resolved
(Xilinx Answer 53971)XST Synthesis not supported in Vivado tool flow v2.6NA
(Xilinx Answer 53314)7 Series - Slack Violations sometimes seen on short paths v2.6Work-around in answer record
(Xilinx Answer 52531)7 Series - Timing errors sometimes seen on path to and from Transceiver v2.5Work-around in answer record
(Xilinx Answer 50809)Updated XDC constraints maybe neededv2.4v2.4rev2
(Xilinx Answer 68299)Timing failures maybe seen in certain casesv2.4v2.5
NA10GBASE-KR Auto-Negotiation not supported in Vivado 2012.1 softwarev2.3v2.4
(Xilinx Answer 47666)Vivado 2012.1 - Guidance for Simulating Ethernet IP coresv2.3NA




AR# 47698
日期 12/15/2016
状态 Active
Type 版本说明
People Also Viewed