AR# 47724


ModelSim - Fatal: (vsim-3729) for mixed-language PCIe example design


The following error is seen when running functional simulation of the PCIe example design in ModelSim.

Loading unisim.mmcme2_adv(mmcme2_adv_v)
# ** Fatal: (vsim-3729) Value ?(1095521093) of generic "clkfbout_use_fine_ps" is out of range false (0) to true (1).
# Time: 0 ps Iteration: 0 Instance: /pcie_rc_rp_testbench_modified/rp/sim_ver20/reggen_to_pcie_rc_for_sim_2/xilinx_rc_sel/xilinx_pcie_rc_modified_sel/gt_top_i/pipe_wrapper_i/pipe_clock_int/pipe_clock_i/mmcm_i File: /eva/fpga/xilinx/13.4/ISE_DS/ISE/vhdl/src/unisims/primitive/MMCME2_ADV.vhd Line: 125
# FATAL ERROR while loading design

Why does this occur and how can I resolve it?


The range mismatch can occur due to an incorrect order of library loading in a mixed-language design.

For example, you might set the language as VHDL and simulation needs to compile both VHDL and Verilog source files. 

In the generated ModelSim simulation script (, the order is expected to be unisims_ver prior to unisim.

vlog -work work -sv +incdir+../../source \
+define+SIMULATION \
$env(XILINX)/verilog/src/glbl.v \
-f board_vlog.f

vcom -work work -f board.f

vsim -voptargs="+acc" +notimingchecks -L work \
-L unisims_ver -L unimacro_ver \
-L unisim -L unimacro -L secureip -t "1ps" \
glbl \

If you use your own script and it specifies "-L unisim" first, the error will occur.

AR# 47724
日期 03/23/2015
状态 Active
Type 综合文章
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