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AR# 47749

2012 Vivado - IP Flows Known Issues


This answer record contains known issues for Vivado Design Suite 2012.x related to IP core flows, including IP customization, IP generation, IP Packager, IP Catalog and integration of IP cores in the Vivado design environment.


Outstanding IP Flow Issues in Vivado Design Suite 2012.3
(Xilinx Answer 47719) - CORE Generator tool issues errors for disabled ports with drivers when generating a unified IP
(Xilinx Answer 51549) - IP Catalog is incorrectly available when a Vivado netlist project is open
(Xilinx Answer 52729) - Attempting to cancel an update of the IP catalog is unsuccessful 
(Xilinx Answer 52760) - DDS Compiler V5 does not get migrated properly as part of a migrated ISE project

IP Flow Issues Resolved in Vivado Design Suite 2012.3
(Xilinx Answer 45489) - CORE Generator tool treats source file with a ".txt" extension as VHDL when packaged with IP Packager
(Xilinx Answer 50988) - Vivado tool fails to upgrade an IP core generated with CORE Generator tool if the coregen.cgc file exists in the same directory as the IP core file
(Xilinx Answer 50990) - IP Upgrade is not available for legacy IP core where the IP version has been removed from the install image
(Xilinx Answer 51491) - Specifying nets as "Data Only" in Debug window causes Abnormal program termination
(Xilinx Answer 51997) - Adding debug cores has the potential to error out due to the 260 Character path limit
(Xilinx Answer 52207) - Module naming conflict may exist when using multiple variations of some IP cores
(Xilinx Answer 52755) - IP License Status dialog shows "Contacting License Server" error when no IP license found
(Xilinx Answer 52757) - Vivado issues CRITICAL WARNING for all 14.2 planAhead projects that instantiate old versions of MVI Video cores 
(Xilinx Answer 52758) - Upgrading Cordic core from 4.0 to 5.0 native doesn't copy the "Compensation Scaling" setting
(Xilinx Answer 52759) - Attempting to synthesize and AXI BFM IP core does not give a clear message why this is not supported
(Xilinx Answer 52772) - A project with an IP core get a run status marked out of date when the project is closed and reopened



Answer Number 问答标题 问题版本 已解决问题的版本
47397 Vivado Design Suite 2012 - Known Issues N/A N/A
AR# 47749
日期 04/28/2014
状态 Archive
Type 已知问题
  • Vivado Design Suite - 2012.2