This answer record discusses the 7 series FPGAs GTX Transceiver power-up/power-down sequencing recommendations and its implications.
1) Recommended power-up/power-down sequence:
The recommended GTX transceiver power-on sequence is VCCINT, VMGTAVCC, VMGTAVTT or VMGTAVCC, VCCINT, VMGTAVTT to achieve minimum current draw. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped up simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw.
If the recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down:
2) For the 7 Series GTX Transceiver General ES Silicon ONLY:
Please note that this section does not apply to GTX Production silicon.
2 a) If the recommended power sequences are not met, then the GTX transceiver can become inoperative if both of the following conditions occur at the same time:
An additional 100 mA per transceiver is drawn from VMGTAVTT when VMGTAVTT is within its recommended operating range and VMGTAVCC is at a voltage of 0.4V or less.
2 b) If the recommended power-up sequence is followed, while VMGTAVCC is powered within its recommended operating range and VMGTAVTT is below 0.7V, an additional 50 mA per GTX transceiver is drawn from VMGTAVCC. Depending on the number of transceivers used, this extra current could be greater than reported in XPE.
Follow this procedure to determine if the power supply regulator for VMGTAVCC is sufficient:
Table 1: Virtex-7 FPGA GTX/GTH Transceiver Power Supply Grouping Per Package
Table 2: Total GTX VMGTAVCC Current for Number of QUADs in a Power Supply Grouping
Number of QUADs in a Power Supply Group
VMGTAVCC Current per Power Supply Group (mA)
3) Frequently Asked Questions
1) What should these additional currents be added to when not following the recommended sequences?
For GTX Production Silicon, this assumes that XPE 14.2 version or newer is used. For GTX General ES silicon, this assumes that XPE 13.4 version or newer is used.
2) Simultaneous power-up: Is it okay to simultaneously power-up VMGTAVCC and VMGTAVTT, OR VCCINT and VMGTAVTT, OR all three? Does the additional current draw still apply?
If these conditions cannot be met, then the additional current needs to be accounted for.
3) Are these additional currents on VMGTAVTT cumulative when both sequences of VMGTAVTT vs VMGTAVCC and VMGTAVTT vs VCCINT are not followed?
The power supply current increase is cumulative. So, if both conditions occur simultaneously, the total is 510mA (460 mA + 50 mA) extra on VMGTAVTT for Production silicon and 610 mA (460 mA + 50 mA + 100 mA) extra on VMGTAVTT for General ES silicon when conditions in section 2.1 also apply.
4) What is the impact of this additional current and when does this happen?
This additional current happens only on the power-up and power-down ramp. Once the GTX transceivers are powered up and running, then this has no impact.
5) What are the key things to keep in mind for the recommended power sequencing to avoid the additional current draw?
VMGTAVTT must be powered up last. VMGTAVCC and VCCINT must be powered up before VMGTAVTT but they can be in any order. VMGTAVCCAUX has no recommended sequencing. These are the criterion that ensure the recommended sequencing is met and there is no current draw.
|10/20/2016||Added conditions for additional current draw during power-down|
|07/23/2012||More clarification added; updated with information on additional current draw when following recommended sequence, duration of current draw, simultaneous power-up and more FAQs.|