AR# 47862

7 Series Integrated Block for PCI Express v1.5 (ISE 14.1/Vivado 2012.1) - Download, Installation and Usage Instructions

描述

ISE 14.1 and Vivado 2012.1 Design Suites contain v1.4 of the 7 Series Integrated Block for PCI Express core. Some of the known issues in v1.4 have been fixed in v1.5. This answer record providesa link to download the v1.5 of the 7 Series Integrated Block for PCI Express core and also describes the installation and usage steps in ISE 14.1 and Vivado 2012.1 Design Suites.

For other Known Issues on 7 Series Integrated Block for PCI Express v1.5: See (Xilinx Answer 40469)

解决方案

1. Download the 7 series Integrated Block for PCI Express v1.5 ZIP file (Xilinx_Answer_47862_pcie_7x_v1_5_rtf.zip) from the link at the end of this solution. Extract the file to a designated location for Custom IPs (IP Repository).

2. Source the IP Repository

GUI Users:

Open Vivado/CORE Generator and point the user repository to the top level of the directory structure.

  • To load the IP in CORE Generator, select Manage IP Catalog under the Manage IP Menu.
  • To load the IP in Vivado, click on IP Catalog, expand Standard Bus Interfaces to select the core.
  • Right click on the core and click on Update IP Catalog.

CORE Generator Batch Users, run:

setenv MYXILINX "path to <corename_rtf>"

Vivado TCL Users, run:

set_property ip_repo_paths "path to <corename_rtf>" [current_fileset]
update_ip_catalog -rebuild

3. Customize and Generate IP

GUI Users:

Select version v1.5 when generating the core.

Vivado Batch Users:

Put version as 1.5 in create_ip command

For example: create_ip -vendor xilinx.com -library ip -name pcie_7x -version 1.5 -module_name core

CORE Generator Batch Users:

Put version as 1.5 in the .xco file

For example: SELECT 7_Series_Integrated_Block_for_PCI_Express xilinx.com:ip:pcie_7x:1.5

Revision History

05/14/1012 - Initial Release

附件

文件名 文件大小 File Type
Xilinx_Answer_47862_pcie_7x_v1_5_rtf.zip 4 MB ZIP

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AR# 47862
日期 03/02/2013
状态 Active
Type 已知问题
Tools