UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47868

LogiCORE SPI-4.2 (POS-PHY L4) - DRC Error when TSClk uses Global Clocking and Performance >= 1 Gb/s

描述


When implementing a SPI-4.2 core for Virtex-6, Kintex-7 or Virtex-7 design with a core configuration that uses TSClk clock distribution = global clocking and Performance >= 1Gbps, you may get the following DRC error:

Error
Invalid attribute value - <no location>
The configured VCO frequency is out of range for Cell pl4_src_clk0/mmcm1. Valid FVCO range varies depending on speed grade: 600MHz - 1200MHz(-1), 600MHz - 1440MHz(-2), 600MHz - 1600MHz(-3). The computed FCVO is a function of the input frequency CLKIN1_PERIOD, the division factor DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F attribute (FVCO = 1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). The CLKIN1_PERIOD attribute is set to the clock constraint value on the CLKIN1 period or can be set as an attribute in HDL. Please adjust the CLKIN1_PERIOD, CLKFBOUT_MULT_F or DIVCLK_DIVIDE attributes to configure the Cell's VCO frequency to be within the valid range.
Related violations: <none>

解决方案

1. Open the pl4_src_clk.v/vhd file and edit the attribute to the MMCM that generates the internal TSClk (instance name mmcm1).
2. Change the CLKFBOUT_MULT_F and CLKOUT0_DIVIDE_F value from 9 to 7.
AR# 47868
日期 05/29/2012
状态 Active
Type 综合文章
器件
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Virtex-7
  • Virtex-7 HT
  • Kintex-7
  • ??????
  • Less
IP
  • SPI-4 Phase 2 Interface Solutions
  • ??????
的页面