AR# 47907


7 Series Integrated Block for PCI Express v1.5 (Vivado 2012.1) - VHDL Root Port Configuration Support


Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

The 7 series Integrated Block for PCI Express v1.5 core supports Root Port configuration but with certain limitation as listed below:

  • Verilog RootPortConfiguration - Both Implementation and Simulation supported
  • VHDL Root Port Configuration - Only Simulation is supported in this release


This is a known issue to be fixed in the next release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/14/2012 - Initial release



AR# 47907
日期 07/23/2012
状态 Active
Type 已知问题
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