We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4791

FPGA Express: Clock buffers cannot be assigned on INOUT ports in Express Constraints Editor


Keywords: inout, Express, Foundation, clock, constraint, don't use, buffer

Urgency: Standard

General Description:
In versions of FPGA Express and FPGA Compiler II up to and including 3.3.1, clock buffers cannot be
assigned or deassigned in the Constraints Editor. Under the ports tab, when the pulldown arrow is
clicked, no options are available.


If you wish to assign a clock buffer on the input side of the bidirectional port, the best solution is to
instantiate this buffer in your HDL source.

If Express / Compiler II is inserting a clock buffer where you do not wish to have one, change the value
on the default (top) line of the Global Buffer column from AUTOMATIC to DONT USE. Then, assign any
clock buffers to normal inputs or instantiate needed clock buffers in your HDL source.
AR# 4791
日期 08/11/2003
状态 Archive
Type 综合文章