General Description: In versions of FPGA Express and FPGA Compiler II up to and including 3.3.1, clock buffers cannot be assigned or deassigned in the Constraints Editor. Under the ports tab, when the pulldown arrow is clicked, no options are available.
If you wish to assign a clock buffer on the input side of the bidirectional port, the best solution is to instantiate this buffer in your HDL source.
If Express / Compiler II is inserting a clock buffer where you do not wish to have one, change the value on the default (top) line of the Global Buffer column from AUTOMATIC to DONT USE. Then, assign any clock buffers to normal inputs or instantiate needed clock buffers in your HDL source.