This answer record contains a list of answer records related to the Zynq-7000 AP SoC errata items.
These Zynq-7000 Errata documents are accessible from the Zynq-7000 Product Support and Documentation page except where noted with limited distribution.
In the table below: Under the Resolution heading, 'fixed' means the issue it not present in one or more production devices.
'TBD' means the issue is under evaluation or a fix is being attempted.
No plan to fix' means the user should assume that the issue will not be fixed.
Under the Affected Devices heading, each column reflects the status of one or more silicon devices:
An 'X' means the item applies to the silicon. 'na' means the issue does not apply.
Note: The information in this answer record (AR) and in the individual answer records is informal and is an attempt to provide accurate and complete information.
All of the information in the answer records is subject to change in order to make corrections, improvements, and reflect changes in our development.
Refer to the appropriate errata document (EN) for each Zynq device.
Key Zynq Links: Product Page | Solution Center | Documents | Boards | PetaLinux
| Answer Record Reference/Link | Category, Issue Title | Resolution | Affected Devices | ||
| Z-7020 CES | Z-7045 CES | Z-7010, Z-7015, | |||
| Boot IOP | |||||
| (Xilinx Answer 44330) | NAND Boot Width is Limited to 8 Bits | fixed | X | na | na |
| (Xilinx Answer 47571) | FSBL Golden Image Search might Fail | fixed | X | na | na |
| (Xilinx Answer 47572) | BootROM might Hang if a NAND Boot Image is Malformed or Corrupted | fixed | X | na | na |
| (Xilinx Answer 47573) | BootROM Floats Boot Device I/O Interface Signals | fixed | X | na | na |
| (Xilinx Answer 47593) | During NOR Boot, MIO Pins 2 and 14 are Inadvertently configured by BootROM | fixed | X | X | na |
| (Xilinx Answer 47594) | During NOR Boot, MIO pin 1 is set to Address bit 25 | fixed | X | X | na |
| (Xilinx Answer 47595) | During Quad-SPI Boot, Image Search for dual SS, 8-bit (dual 4-bit) Parallel is performed in 64 kB steps | fixed | X | X | na |
| (Xilinx Answer 47597) | Micron 8Gb (on-die ECC) NAND devices do not work | fixed | X | X | na |
| (Xilinx Answer 47598) | BootROM stops searching for boot image after first 16 MBs for Quad-SPI x8 and SRAM/NOR | fixed | X | X | na |
| (Xilinx Answer 51907) | SDIO Boot runs at low frequency and data width | fixed | X | X | na |
| (Xilinx Answer 52014) | Quad-SPI MIO pin 8 is inadvertently enabled during boot | fixed | X | X | na |
| (Xilinx Answer 52016) | SDIO boot mode inadvertently uses Card Detect on MIO pin 0 | fixed | X | na | na |
| Boot Sys | |||||
| (Xilinx Answer 47567) | Program Counter (PC) of CPU 1 Points to an Invalid Address when Booting from JTAG | fixed | X | na | na |
| (Xilinx Answer 47568) | BootROM Error Codes are not Unique | fixed | X | na | na |
| (Xilinx Answer 47569) | PS-PL AXI Interfaces are Enabled upon Completion of the BootROM | fixed | X | na | na |
| (Xilinx Answer 47570) | SLCR Registers are not Locked upon Completion of the BootROM | fixed | X | na | na |
| (Xilinx Answer 47574) | MIO Pins are not Three-Stated when ErrorLockDown Occurs | fixed | X | na | na |
| (Xilinx Answer 47588) | MultiBoot feature is not supported. | fixed | X | X | na |
| (Xilinx Answer 47599) | Independent JTAG is not supported in JTAG Boot mode | fixed | X | X | na |
| (Xilinx Answer 52012) | INIT_B pin does not indicate boot error status | fixed | X | X | na |
| (Xilinx Answer 52013) | PS_SRST_B asserted during a POR boot does not result in a secure lockdown | fixed | X | X | na |
| (Xilinx Answer 52030) | Reset Reason Mechanism does not use slcr.REBOOT_STATUS register | fixed | X | X | na |
| (Xilinx Answer 55329) | BootROM 128-KB CRC self-check is not supported | fixed | X | X | na |
| Clocks | |||||
| (Xilinx Answer 47525) | Soft Reset of System Clocks does not Consistently Reset Clock Dividers to Default Values | fixed | X | na | na |
| Debug | |||||
| (Xilinx Answer 47527) | ITM and FTM Frames might be Indistinguishable by Software | fixed | X | na | na |
| (Xilinx Answer 52022) | System Debug Reset does not work | fixed | X | X | na |
| Device ID | |||||
| (Xilinx Answer 47317) | Incorrect PS Family IDCODE Value | fixed | X | na | na |
| DDR | |||||
| (Xilinx Answer 47512) | LPDDR2 Dynamic Clock Stop Restarts too soon | fixed | X | X | na |
| (Xilinx Answer 47514) | DDR3 Starts DRAM Clock too Early after Exiting Self-Refresh | fixed | X | na | na |
| (Xilinx Answer 47516) | Controller Mishandles STREX Instruction | fixed | X | na | na |
| (Xilinx Answer 47521) | DCI Quiet Mode Operation is not Supported | fixed | X | na | na |
| (Xilinx Answer 47522) | DCI Does not Work | fixed | X | na | na |
| (Xilinx Answer 47564) | DDR I/O Buffers (DDRIOB) do not Support External VREF | fixed | X | na | na |
| (Xilinx Answer 47576) | Automatic ZQ Calibration is not Supported in LPDDR2 Mode | fixed | X | X | na |
| (Xilinx Answer 47580) | LPDDR2 Per-Bank Refresh is not Supported | No plan to fix | X | X | X |
| (Xilinx Answer 47581) | Read Operations Malfunction when they Follow an MRW within 128 DDR Clocks | No plan to fix | X | X | X |
| (Xilinx Answer 47582) | In LPDDR2 Mode, ZQCL Command is not Issued after Self-Refresh Exit | fixed | X | X | na |
| (Xilinx Answer 52021) | Read Gate Training value is unreliable in Slice 3 | fixed | X | X | na |
| GigE | |||||
| (Xilinx Answer 52019) | Ethernet TxDMA can hang | fixed | X | X | na |
| (Xilinx Answer 52025) | Unicast And Broadcast Pause Frames Received By The Controller Are Not Filtered Out | No plan to fix | X | X | X |
| (Xilinx Answer 52026) | Back-off Time Is More Aggressive Than The Standard Requirement | No plan to fix | X | X | X |
| (Xilinx Answer 52027) | Packets Up To 1,536 Bytes Are Allowed With VLAN Tagging | No plan to fix | X | X | X |
| (Xilinx Answer 52028) | Receive Path Lock-Up Might Occur When A Large Number Of Receive Resource Errors Are Generated | No plan to fix | X | X | X |
| Interconnect | |||||
| (Xilinx Answer 47484) | Deadlock can Occur when OCM and DDR are Accessed by AXI_HP | fixed | X | na | na |
| (Xilinx Answer 47544) | OCM Interconnect Switch can Experience Starvation with Heavy CPU/ACP Traffic | fixed | X | X | na |
| Programmable Logic | |||||
| (Xilinx Answer 47578) | PL Readback Operation of the Bitstream through the DevC Interface does not Work | fixed | X | X | na |
| (Xilinx Answer 51123) | SEU Readback enabled by POST_CRC=ENABLE is not supported | fixed | X | na | na |
| Power | |||||
| (Xilinx Answer 47592) | Static Power is higher than Reported | fixed | X | X | na |
| SPI / Quad-SPI | |||||
| (Xilinx Answer 47511) | SPI Master Mode on MIO will Reset the controller when the SS0 Signal Asserts | fixed | X | na | na |
| (Xilinx Answer 47575) | Quad-SPI and SPI RxFIFOs Not Empty Status' are not Updated Promptly | No plan to fix | X | X | X |
| (Xilinx Answer 47577) | Quad-SPI Controller in Linear Addressing Mode might Hang in a Highly Loaded System | fixed | X | na | na |
| (Xilinx Answer 47579) | SPI master mode setup timing is dependent on the SPI reference clock period | fixed | X | na | na |
| (Xilinx Answer 47596) | Quad-SPI controller does not drive HOLD_B inactive during SPI data phase | fixed | X | na | na |
| (Xilinx Answer 52015) | Quad-SPI register LPBK_DLY_ADJ must be Manually set to 0 | fixed | X | X | na |
| (Xilinx Answer 60978) | QSPI Controller Reports Wrong Busy Status Of Flash Memories In Dual Parallel Configuration When Auto CS And Divide by 2 Baud Rate Is Used | No plan to fix | X | X | X |
| SDIO | |||||
| (Xilinx Answer 47529) | SD Capability Register Shows Wrong Max_Block_Length Value | fixed | X | na | na |
| (Xilinx Answer 47531) | ADMA2 Mode Burst Transactions Alignment and Length Requirements | No plan to fix | X | X | X |
| (Xilinx Answer 47532) | Software Reset Sequence to Avoid Interconnect Hang | No plan to fix | X | X | X |
| (Xilinx Answer 47533) | Second CMD12 can be Erroneously Issued if Auto CMD12 is Enabled | No plan to fix | X | X | X |
| (Xilinx Answer 47534) | ADMA2 Mode Fails to Release Properly when Abort CMD is Issued | No plan to fix | X | X | X |
| (Xilinx Answer 47535) | Transfer Complete Asserts before Completing Busy due to CMD13 | No plan to fix | X | X | X |
| (Xilinx Answer 47536) | CMD13 not Handled Properly when CMD19 is in Progress | No plan to fix | X | X | X |
| (Xilinx Answer 47537) | ADMA2 Read Corrupts Data that was Written Using PIO Mode | fixed | X | na | na |
| (Xilinx Answer 52020) | CMD17 may not complete | fixed | X | X | na |
| (Xilinx Answer 52023) | Controller does not Wait 74 clock cycles to Issue CMD0 | fixed | X | X | na |
| Security | |||||
| (Xilinx Answer 47530) | PL can Retain Configuration through a Reset Cycle | fixed | X | na | na |
| (Xilinx Answer 47565) | Secure Boot Features are not Supported | fixed | X | X | na |
| (Xilinx Answer 47566) | JTAG Chain is Accessible before the BootROM Completes | fixed | X | na | na |
| (Xilinx Answer 52017) | Register Initialization During BootROM Handover does not Error on Illegal Addresses | fixed | X | X | na |
| Signals | |||||
| (Xilinx Answer 47873) | MIO Interface Signal Logic Levels can be Observed by GPIOs | fixed | X | na | na |
| (Xilinx Answer 47874) | SDIO Three-State Enable Signals on EMIO have the Wrong Polarity | fixed | X | na | na |
| SMC | |||||
| (Xilinx Answer 47517) | NAND with ECC might not Deassert CS between Data Transactions | No plan to fix | X | X | X |
| (Xilinx Answer 47518) | Potential SRAM/NOR Data Error | No plan to fix | X | X | X |
| (Xilinx Answer 47519) | NAND with ECC Misses Single Bit and some Double Bit Errors | fixed | X | X | na |
| (Xilinx Answer 47520) | NAND ECC Status Register can Incorrectly Report a Failure for One Clock Cycle | No plan to fix | X | X | X |
| (Xilinx Answer 61637) | SMC Parallel (SRAM/NOR) Interface Does Not Correctly Assert CS0 For 64 MB Memories | No plan to fix | X | X | X |
| (Xilinx Answer 61638) | SMC Parallel (SRAM/NOR) Interface Address Bit 25 Is Inverted For 64 MB Memories | No plan to fix | X | X | X |
| Timers | |||||
| (Xilinx Answer 47545) | Global Timer can Send Two Interrupts for the Same Event | No plan to fix | X | X | X |
| USB | |||||
| (Xilinx Answer 47538) | OTG in Device Mode Does not Generate a Port Change Interrupt when Session is no Longer Valid | No plan to fix | X | X | X |
| (Xilinx Answer 47539) | Suspend Bit is Asserted before the Port Enters the Suspend State | No plan to fix | X | X | X |
| (Xilinx Answer 47540) | First SOF after a Software Reset can be Corrupted | No plan to fix | X | X | X |
| (Xilinx Answer 47541) | In HS Host Mode, NYET Decrements NAK Counter | No plan to fix | X | X | X |
| (Xilinx Answer 47543) | ULPI Viewport does not Work with Extended Addresses | No plan to fix | X | X | X |
| (Xilinx Answer 51121) | Adding a dTD to a Primed Endpoint might not get Recognized | fixed | X | X | na |
| Application Processing Unit (APU) | |||||
| (Xilinx Answer 47546) | Processor might miss Watchpoint on Second Part of Unaligned Access Crossing Page Boundary | No plan to fix | X | X | X |
| (Xilinx Answer 47547) | Following an ASID Switch, Faulty MMU Translations can Occur | No plan to fix | X | X | X |
| (Xilinx Answer 47548) | Ordering of Read Accesses to the Same Memory Location Might not be Ensured | No plan to fix | X | X | X |
| (Xilinx Answer 47549) | System Deadlock can occur in SMP Mode when the Same Cache Line is Accessed by Both CPUs and the ACP | No plan to fix | X | X | X |
| (Xilinx Answer 47550) | Cache Line Maintenance Operations by MVA might not Succeed on an Inner Shareable Memory Region | No plan to fix | X | X | X |
| (Xilinx Answer 47551) | ISB Instruction is Counted in Performance Monitor Events 0x0C and 0x0D | No plan to fix | X | X | X |
| (Xilinx Answer 47552) | ARM MainID Registers are not Aliased to Debug Interface on APB | No plan to fix | X | X | X |
| (Xilinx Answer 47553) | ARM Debug Execution Stalls when an Instruction is Written to the ITR Following an Aborted Load/Store | No plan to fix | X | X | X |
| (Xilinx Answer 47554) | Debug Program Counter Sampling (DBGPCSR) Register Format is Incorrect | No plan to fix | X | X | X |
| (Xilinx Answer 47555) | Imprecise Abort can be Reported Twice on Non-Cacheable Reads | No plan to fix | X | X | X |
| (Xilinx Answer 47556) | Repeated CPU Store Instructions within same Cache Line can Delay Visibility of the Store | No plan to fix | X | X | X |
| (Xilinx Answer 47557) | Sticky Pipeline Advance Bit is not Supported | No plan to fix | X | X | X |
| (Xilinx Answer 47558) | Unallocated Memory Hint Instruction can Generate an Undefined Exception Instead of Being Treated as a NOP | No plan to fix | X | X | X |
| (Xilinx Answer 47559) | MRC and MCR Instructions are not Counted in Event 0x68 | No plan to fix | X | X | X |
| (Xilinx Answer 47560) | Read Accesses to a DBGPRSR or DBGOSLSR Register by the DAP Controller can Generate an Unexpected Undefined Exception | No plan to fix | X | X | X |
| (Xilinx Answer 47561) | High Priority for SO and Dev Reads Feature can Cause QoS Issues to Cacheable Read Transactions | No plan to fix | X | X | X |
| (Xilinx Answer 47562) | A Continuous Write Flow can Stall a Read Targeting the Same Memory Area | No plan to fix | X | X | X |
| (Xilinx Answer 47563) | L2 Cache Controller can Prefetch Across 4 KB Boundary with Offset set to 23 | No plan to fix | X | X | X |
| (Xilinx Answer 47584) | PLD Instructions might Allocate even in a Disabled Data Cache | No plan to fix | X | X | X |
| (Xilinx Answer 47585) | Visibility of Debug Enable Access Rights to Enable/Disable Tracing is not Ensured by an ISB Instruction | No plan to fix | X | X | X |
| (Xilinx Answer 47586) | Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor, can Lead to Livelock | No plan to fix | X | X | X |
| (Xilinx Answer 47587) | Parity Errors on BTAC and GHB are Always Reported Regardless of the Parity Enable Bit Setting | No plan to fix | X | X | X |
| (Xilinx Answer 51122) | Strongly Ordered Write Followed By LDREX Might Deadlock Processor | No plan to fix | X | X | X |
| (Xilinx Answer 52031) | A data cache maintenance operation which aborts, followed by an ISB, without any DSB in-between, might lead to deadlock | No plan to fix | X | X | X |
| (Xilinx Answer 52032) | Short loop with a DMB might cause a denial of service on another Processor that is attempting to execute a CP15 broadcast operation | No plan to fix | X | X | X |
| (Xilinx Answer 52033) | Speculative instruction fetches with MMU disabled might not comply with architectural requirements | No plan to fix | X | X | X |
| (Xilinx Answer 52034) | A write request to Uncacheable, Shareable normal memory region might be executed twice, possibly causing a software synchronization issue | No plan to fix | X | X | X |
| (Xilinx Answer 52035) | Updating a translation entry to move a page mapping might erroneously cause an unexpected translation fault | No plan to fix | X | X | X |
| (Xilinx Answer 52036) | CPU performance monitor event 0x0A might count twice the LDM PC ^ instructions | No plan to fix | X | X | X |
| (Xilinx Answer 55018) | A spurious event 0x63, STREX passed, might be reported on an LDREX | No plan to fix | X | X | X |
| (Xilinx Answer 55325) | Possible denial of service for coherent requests on an L1 cache line which is continuously written by a processor | No plan to fix | X | X | X |
| (Xilinx Answer 55326) | A branch-to-self instruction in the last L1 cache line of a page might cause a denial of service | No plan to fix | X | X | X |
| (Xilinx Answer 55327) | Write Context ID event in a CPU is updated on read access | No plan to fix | X | X | X |
| (Xilinx Answer 55328) | DBGPRSR Sticky Reset status bit is set to 1 by the CPU debug reset instead of by the CPU non-debug reset | No plan to fix | X | X | X |
| I2C | |||||
| (Xilinx Answer 60693) | Fast Mode running faster than 384kHz violates tLOW; STA timing requirement | No plan to fix | X | X | X |
| (Xilinx Answer 60694) | Fast Mode running faster than 384 kHz violates tBUF; STA timing requirement | No plan to fix | X | X | X |
| (Xilinx Answer 60695) | I2C Missing Arbitration on Repeated Start | No plan to fix | X | X | X |
| (Xilinx Answer 59366) | Standard Mode running faster than 90 kHz violates tHD; STA timing requirement | No plan to fix | X | X | X |
| (Xilinx Answer 61664) | I2C Master Generates Invalid Read Transactions | No plan to fix | X | X | X |
| (Xilinx Answer 61665) | Missing I2C Master Completion Interrupt | No plan to fix | X | X | X |
| (Xilinx Answer 61861) | Missing Glitch Filter Implementation | No plan to fix | X | X | X |
Note for Z-7020 9921 ESLAB device (only):
(Xilinx Answer 47590), 'On-Chip Voltage References for ADCs are not accurate' - Only the Z-7020 9921 ESLAB devices (earliest samples) are affected by this errata item.
None of the CES devices or any of the production device types are affected.
Revision History:
September 2014
August 2014
July 2014
September 2013
June/July 2013
May 2013
April 2013
March 2013
February 2013
December 2012
October 2012
| AR# 47916 | |
|---|---|
| 日期 | 06/03/2021 |
| 状态 | Active |
| Type | 设计咨询 |
| 器件 | |