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AR# 47959

13.4 Timing Analysis Virtex-6 - Clock Arrival Times are Incorrect for Block Ram or FIFO Components

描述

When I analyze the timing paths to or from the Block Ram or FIFO, the clock arrival time for either the source or destination clock is incorrect and makes the requirement extra small. I should have a full cycle for these paths. When is this going to be fixed?

解决方案

This issue is resolved in ISE Design Suite 14.1, but you must re-run implementation from NGDbuild.
AR# 47959
日期 05/24/2012
状态 Active
Type 已知问题
器件
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less
Tools
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
的页面