Description

An HDL design with primitive instantiation results in an unexpanded block error during NGDBuild. 

ERROR:basnu:93 logical block of type "RAM16X1D" is unexpanded.

解决方案

A possible cause of this type of unexpanded block error is if the ports of declared primitive component is declared as a bus. 

The ports of all Xilinx primitives have to be single ports. 

The following is an example of correct instantiation for 

RAM16X1D in VHDL: 

--The IEEE standard 1164 package 

library IEEE; 

use IEEE.std_logic_1164.all; 

use IEEE.std_logic_arith.all; 

use IEEE.std_logic_unsigned.all; 

entity RAMD is 

port (wclk,we,d : in std_logic; 

a : in std_logic_vector ( 3 downto 0); 

dpra : in std_logic_vector ( 3 downto 0); 

SPO,DPO : out std_logic); 

end RAMD; 

architecture inside of ramd is 

component RAM16X1D 

port(wclk,we,d,a3,a2,a1,a0,dpra3,dpra2,dpra1,dpra0: in std_logic; 

SPO,DPO: out std_logic); 

end component; 

begin 

U1: RAM16X1D port map (wclk=>wclk,we=>we,d=>d,a3=>a(3),a2=>a(2),a1=>a(1),a0=>a(0), 

dpra3=>dpra(3),dpra2=>dpra(2),dpra1=>dpra(1),dpra0=>dpra(0),SPO=>SPO,DPO=>DPO); 

end inside;

Verilog example: 

-------------------------- 

module RAMD(wclk, we, a, d, dpra, spo,dpo); 

input [3:0] a, dpra; 

input wclk, we, d; 

output [3:0] spo, dpo; 

RAM16X1D U1 (.spo(spo),.dpo(dpo), .d(d), .A3(a[3]), .A2(a[2]), .A1(a[1]), .A0(a[0]), 

.dpra3(dpra[3]),.dpra2(dpra[2]),.dpra1(dpra[1]),.dpra0(dpra[0]), .WE(we), .WCLK(wclk)); 

endmodule

The component/symbol stated in the error message can have a corrupted netlist. Delete the netlist and regenerate it.