UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4855

LogiCORE PCI - How does the PCI CORE handle the insertion of wait states between data phases?

Description

General Description:

How does the PCI CORE handle insertion of wait states between data phases?

解决方案

As a target, the core cannot insert subsequent latency (wait states) between data phases, but it can insert initial latency. The LogiCORE target can handle both initial and subsequent master latency insertion (wait states inserted by the master in the beginning or during a transfer) correctly. This is true for both Target Read and Target Write. Target-initiated wait states allow a user application additional time before the first data transfer.

The user application can de-assert the S_READY output to insert wait states.

The target is required to complete the first data phase of a transaction within 16 clocks from the assertion of FRAME_IO.

For more information on how to insert initial latency, please see the LogiCORE PCI User/Design Guides, which are available at:

http://www.xilinx.com/pci

As a master, the core behaves in the same way as a target. It cannot insert subsequent latency, but is compliant in handling a target that does. It can insert initial latency before the first data phase begins.

The user application can de-assert the M_READY output to insert wait states.

For more information on how to insert initial latency, please see the LogiCORE PCI User/Design Guides, which are available at:

http://www.support.xilinx.com/products/logicore/coredocs.htm#datasheets

The user application can hold the C_READY output Low to insert wait states during configuration read/writes. A target is required to complete the first data phase of the transaction within 16 clock cycles from the assertion of FRAME_IO.

For more information on how to insert initial latency, please see the LogiCORE PCI User/Design Guides, which are available at:

http://www.support.xilinx.com/products/logicore/coredocs.htm#datasheets

AR# 4855
创建日期 08/21/2007
Last Updated 12/15/2012
状态 Active
Type 综合文章