How does the target Core behave in the event that the back-end user application logic is not able to use the "S_READY" signal for the first data phase of a PCI transaction of more than 16 clocks? Does it initiate a target termination sequence on the PCI bus?
The Xilinx core does not automatically terminate the transfer if the back-end application does not assert S_READY within 16 clocks. This gives users much more flexibility.
However, delaying the S_READY signal for a greater amount of time is a violation of the PCI specification. However, for some closed (embedded) systems, this may not be relevant.